Polysilicon gate

Here, it is easy to see the various layers and steps necessary to form the IC. We have already emphasized the formation of the n- and p-wells 8uid the individual proeess steps needed for their formation. Note that an epitaxial layer is used in the above model. There are isolation barriers present which we have already discussed. However, once the polysilicon gate transistors are formed, then metal Interconnects must then be placed in proper position with proper electrical isolation. This is the function of the dielectric layers put into place as succeeding layers on the IC dice. Once this is done, then the wafer is tested. 

Again, double liquid treatments of HMDS did not prove adequate for polysilicon gate substrates, substrates comprised of amorphous deposited silicon as... 

Dopant species can be codeposited with the Si02 by introducing small amounts of the dopants in hydride or halide form. P-doped Si02, called P-glass, functions as an insulator between polysilicon gates and the top metallization layer of ICs. It is also used as a final passivation layer over devices, and as a gettering source (17). 

Step 8. The n+ -type source and drain regions are created by As ion implantation. The As can penetrate the thin gate oxide, but not the thick field oxide or the polysilicon gate. The formation of the source and gate does not require a separate resist pattern, thus this technique is called self-aligning. 

An array which is compact and easy to manufacture is disclosed in JP-A-57031170. A MOSFET with a polysilicon gate electrode is formed in a silicon substrate. A thin HgCdTe film composed of an n-type layer and a p-type layer is prepared on the source. 

Here, 41 indicates the thin film transistors, 51 the substrate, 43 a dielectric layer, 49 polysilicon gates, 50 gate electrodes, 55 contact plugs, 56 bottom electrodes, 53 the planarization layer, 54 the mercury cadmium telluride layer and 57 the top electrode layer. The planarization layer is formed from silicon oxide, silicon nitride, silicon oxide nitride or from a polyimide. The planarization layer may be formed as a double or triple layer. 

F. H. Bell and O. Joubert, Polysilicon Gate Etching in High Density Plasmas. 5. Comparison between Quantitative Chemical Analysis of Photoresist and Oxide Masked Polysilicon Gates Etched in Hbr/Cl-2/0-2 Plasmas, J. Vac. Sci. Technol. 5 15, 88-97 (1997). 

As one can imagine, such a thin insulating layer is prone to electron tunneling between the polysilicon gate and channel, leading to increased power consumption... 

Figure 1. Comparison of conventional polysilicon-gate process to proposed CPI-gate process.

NOTCH- AND FOOT-FREE DUAL POLYSILICON GATE ETCH... 

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