Buried oxide

For the development of SEU-hardened memory devices, it is expedient to reduce charge collected in a memory cell. For this purpose, the formation of buried oxide in device structures, i.e., the fabrication of SOI structure, is considered a useful method because such a buried oxide layer can be expected to suppress the charge collection due to the drift and funneling processes. However, no experimental approach had been made for the charge collection in SOI devices. To investigate the charge collection in the SOI structure, transient currents induced in SOI pn junctions by heavy ions such as 15-MeV carbon (C) or oxygen (O) ions have been measured. 

As illustrated in Fig. 15.11, wafers can be bonded face-to-face, the handle of the SOI wafer can be thinned to stop on the buried oxide layer, rebonded to another handle wafer, thinned again to stop on the bonding layer, and then tested. Lu et al. have used this approach to demonstrate process compatibility on passive structures [85], Gutmann et al. have used this method to demonstrate process compatibility using active electrical structures [49], and... 

The presence of an insulating layer directly beneath a thin Si channel is reported to reduce off-state leakage from source to drain regions by more than two orders of magnitude. When the top of the buried oxide layer (BO c) coincides with the bottom of source/drain, the architecture is referred to as a fully depleted SOB, a small... 

Fio. 2. Diagrammatic representation of a cross section through the (001) plane at the surface of a cuprous oxide crystal. Key O Oxygen atoms Copper atoms — — Protruding oxide surface . Buried oxide surface. 

Another type of integrated micromachined structure different from the anchored polysilicon surface films occurs by adding the micromachined structure to the wafer after the IC is created by plating or film deposition. Texas Instruments DLP technology with aluminum metal is the most well known example [3]. However, these types of structures are not used in large-scale automotive production. Another class of micromachined devices is made from silicon-on-insulator (SOI) components and could easily be described as surface micromachined, since they have mechanical structures on the surface. These devices use the buried oxide of the bonded wafer as the sacrificial layer [6]. A similar structure created by epitaxial deposition of silicon over oxide produces a polysilicon structure [7]. Figure... 

Chen, K.W. et al.. Characterization of nano-sized Si islands in buried oxide layer of SIMOX by conducting AFM, Chem Phys Lett 376, 748-752, 2003. 

The samples were fabricated on a bonded SOI wafer with a 60-70 tun thick SOI film, where the buried-oxide layer was 400 mn thick. The wafer was heavily doped with phosphorous 3.5 - 16 TO cm. The electrons were uniformly heated in the very long (up to 1500 pm) SOI film by applying heating current between the contacts, which were at the ends of the silicon film. The Joule heat was calculated by using the values of the sheet resistance of the film and of the electrical current. A He/" He dilution refrigerator was used for the measvuement in the temperature range between 50 mK and 500 mK. 

Figure 1.12 Silicon on insulator (SOI) wafer that is used in the SOIMUMPS process. The device layer can be 10 1 pm or 25 1 (im thick. The handle wafer is 400 5 pm thick and the buried oxide layer is 1 0.05 pm thick. (Reprinted with permission from MEMSCAP Inc.) See color plate section.

Both etches stop on the buried oxide. (Reprinted with permission from MEMSCAP Inc.) See color plate section. 

Figure 1.13 Patterned SOIMUMPS wafer. Through-wafer etches are performed from the front side of the wafer 10 or 25 pm deep to form device layer holes, and from the back side 400 pm deep to form through-wafer holes. Both etches stop on the buried oxide. (Reprinted with permission from MEMSCAP Inc.)...

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