Wafer silicon-on-insulator

J. Haisma, G. A. C. M. Spierings, U. K. P. Biermann, and J. A. Pals, Silicon-on-insulator wafer honding-wafer thinning technological evaluations, Jpn. J. Appl. Phys. 1426, 1989. 

M. Tajima, S. Ibuka, H. Aga, and T. Abe, Characterization of bond and etch-back silicon-on-insulator wafers by photoluminescence under ultraviolet excitation, Appl. Phys. Lett. 70(2), 231, 1997. 

Silicon Micromachining, Fig. 8 Illustration of the comb-drive stmcture in SOI (silicon-on-insulator) wafer fabricated using surface micromachinmg... 

Wafer bonding is a technology to combine two substrates in order to achieve a mechanically stable connection between them. The technology is apphed for substrate production, for example, for the fabrication of silicon on insulator wafers or compound semiconductor wafers and for device fabrication, for example, for the fabrication of MEMS/MOEMS devices as described in previous sections, for stacking devices in 3D integration, or for wafer-level packaging. 

Figure 13.16 shows a SiNW 4 p.m in length and 9.5 nm in width. Figure 13.16a shows the silicon oxide mask. The thickness of the fabricated mask is about 3 nm. After etching, the SiNW is contacted to two platinum electrodes (Fig. 13.16b). The fabricated SiNW is the main element of a field-effect transistor formed by introducing a gate electrode. Here, the gate electrode is situated at the back of a silicon-on-insulator wafer. The output and transfer characteristics of the transistor formed with the SiNW described above are shown in Fig. 13.16d. The output curve (left panel) shows a clear dependence on the gate voltage. The off-state drain current leakage is about 10 A. The device shown above has an on/off current ratio of 10, and it can be used to develop very sensitive biomolecular sensors.

Y. Mori, K. Yamamura, Y. Sano, 2004, Thinning of Silicon-on-Insulator Wafer by Numerically Controlled Plasma... 

Substrates The substrates in microelectronics are mainly Si wafers. For mobile applications, silicon-on-insulator (SOI) wafers increasingly replace bulk Si wafers and for very specific high-frequency applications, III-V compound semiconductors (e.g., GaAs) are used. The majority of substrates in microfabrication are Si wafers, but metal, glass, and ceramic substrates are also common. Particularly when using glass, quartz, and ceramic wafers in CMP processes, it has to be taken into account that they are brittle and easy to break. The situation is worse when the material is also under stress induced by deposited layers. For applications where the backside of the wafer has to be structured (e.g., in bulk micromachining), double-side polished substrates are employed. 

Figure 4.23. Two methods used to fabricate silicon-on-insulator (SOI) wafers. Illustrated are the (a) Smartcut procedure where two oxidized wafers are bonded together and (b) SIMOX procedure where oxygen ions are implanted into a bulk Si wafer.

W. P. Maszara, Silicon-on-insulator by wafer bonding Review, J. Electrochem. Soc. 138, 341, 1991. 

Silicon fusion bonding has been extensively studied during the past few years not only for sensor applications, but also because it represents a good alternative for the fabrication of high quality silicon-on-insulator (SOI) wafers [39]. 

Another type of integrated micromachined structure different from the anchored polysilicon surface films occurs by adding the micromachined structure to the wafer after the IC is created by plating or film deposition. Texas Instruments DLP technology with aluminum metal is the most well known example [3]. However, these types of structures are not used in large-scale automotive production. Another class of micromachined devices is made from silicon-on-insulator (SOI) components and could easily be described as surface micromachined, since they have mechanical structures on the surface. These devices use the buried oxide of the bonded wafer as the sacrificial layer [6]. A similar structure created by epitaxial deposition of silicon over oxide produces a polysilicon structure [7]. Figure... 

Motorola Z-axis accelerometer [21], f) Motorola Folded-beam Z-axis accelerometer, g) Motorola X-lateral accelerometer (an Analog Devices surface micromachined lateral accelerometer is shown in Fig. 7.1.1 a) h) epi-poly-silicon surface micromachining [93] i) silicon on-insulator surface micromachining [94] j) bonded wafer [69, 95] k) nickel electroplated [96]... 

To make the 2 nm Si02 nanopores, the typical process starts with a silicon-on-insulator (SOI) wafer. The silicon substrate is anisotropi-cally etched by KOH to leave a small region of freestanding silicon film. E-beam lithography is then performed to create a hole in the device silicon layer, and the size of the hole is further reduced by thermal oxidation to grow a layer of Si02 from the device layer silicon. This process will lead to a nanopore of less than 20 nm diameter, which is subsequently shrunk to 2-3 nm in a transmission electron microscope by focus electron beam-mediated reflow of the Si02. 

Lasky JB (1986) Wafer bonding for silicon-on-insulator technology. Appl Phys Lett 48 78-80... 

Silicon-on-insulator (SOI) wafers 3 Waffle solar cells 7... 

Step 1 We start by choosing a suitable substrate—a silicon-on-insulator (SOI) wafer. An SOI wafer consists of a thin (1 pm or less) Si02 layer sandwiched between two Si layers. We first thermally grow 1 pm of Si02. 

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