Silicone Poly

Mulder, J., Eppenga, P., Hendriks, M., and Tong, J., An Industrial LPCVD Process for In Situ Phosphorus-Doped Poly silicon, /. Electrochem. Soc., 137(l) 273-279(Jan. 1990)... 

Replacement for poly silicon gates and interconnects in MOS devices. 

Polysilicon is a contraction of polycrystalline silicon, (in contrast with the single-crystal epitaxial silicon). Like epitaxial silicon, polysilicon is also used extensively in the fabrication of IC s and is deposited by CVD.f l it is doped in the same manner as epitaxial silicon. Some applications of poly silicon films are ... 

C.I. Silicon and Poly silicon. The isotropic etching of silicon (Si) and polycrystalline silicon (Poly-Si) by atomic fluorine (F) is probably the most completely understood of all etch processes, particularly for the cases in which F atoms are produced in discharges of F2 (36) and CF4/O2 (42). Fluorine atoms etch (100) Si at a rate (A/min) given by (36) ... 

Figure 20, Reflectivity variations during the etching of a poly-silicon film on an Si02 substrate, (Reproduced with permission from Ref, 110,)...

Figure 17. SEM photo miocrographs of GeSe/HPR206 bilevel patterns generated by contact printing over the poly silicon level of a 16K MOS RAM wafer. (Reproduced with permission from Ref. III).

Another case of bridging was also reported recently in a neutral poly-silicon complex, and is discussed in the section on neutral pentacoordinate complexes (Section III.C.2). 

A piezoelectric pump is constructed with two glass plates and a silicon wafer [22]. A pressure chamber and a raised flat surface suspended with a thin diaphragm are formed on the upper glass plate (Fig. 3). The piezoelectric actuator is placed on the raised flat surface. In order to guide the flow of the pumped liquid, two check valves made of poly-silicon are fabricated on the silicon wafer... 

Fig. 3. Structure and principle of the piezoeletric micropump using poly-silicon check valves...

In the selection of etch mask for deep glass etching, thick SU-8 is a choice, but SU-8 cannot be used in a HF bath (48%) because SU-8 does not adhere well to Si02 [123]. However, with a polycrystalline amorphous Si seed layer SU-8 adheres very well. For instance, with a 1.5-pm-thick polished poly silicon, a 50-pm-thick SU-8 can be deposited as the etch mask, leading to a maximum etch depth of 320 pm. Usually photoresist (2 pm thick) is only useful for shallow etch, less than 50 pm [123]. 

Polished or unpolished polysilicon (by low-pressure CVD at 620°C) is another etch mask option. Utilizing 2.5-pm-thick unpolished polysilicon, a maximum etch depth of 160 pm was reached using a HF/H20/HN03 (6 40 100) solution. Further etching causes large pits (1.5-2.2 mm dia.) to form on the glass. With polished poly silicon (1.5 pm thick), etch depth up to 250 pm can be achieved. When amorphous Si is used as the etch mask, a maximum etch depth of 170 pm can be reached [123]. 

Hong YK, Kang YJ, Park JG, Han SY, Yun SK, Yoon BU, Hong CK. Effect of poly silicon wettability on organic t5 pe defects in poly CMP. 210th ECS Meeting Cancun Mexico Oct 302005. 

The types of defects existing before polysilicon CMP are similar to the types of defects that can be observed before oxide CMP. The main difference is that the poly-Si film is not as transparent as an oxide film. The thicker the poly silicon film, the less transparent it is. 

Figure 20.14 [13] shows a second method of converting the polygate to silicide for high-k applications. Here again, the CMOS transistors are formed with conventional poly-silicon gates. After ILDO deposition, the surface is polished back to expose the poly-silicon. Metal films are then deposited and... 

AEP ring coupled with Titan Head design and optimized processes has contributed to wide acceptance of the Mirra CMP platform for oxide (PMD and ILD), STI, poly silicon, as well as W CMP applications in IC fabs.[5] The AEP ring along with many other hardware upgrades has also played an important role in successful Cu, SOI, and Si CMP applications on the Mirra CMP platform. [6]... 

S. A. Abbas Silicon on poly silicon with deep dielectric isolation , Proc. of IBM Teclmical Disclosure Bulletin Vol. No.7 Dec. 1997 P.2754... 

Fig. 3. Appearance of silicone organic copolymers left poly[silicone- o>styrene]...

In most types of IC s, the contacts can end on n+ or p+ mono-crystalline silicon, poly-silicon, various types of silicides, and other materials such as TiN. One of the most important properties of the contact and the via is the contact resistance (Rc) ... 

Many of the first papers which discussed the use of (selective) CVD of tungsten for IC applications used conventional hot wall tube CVD reactors [Broadbent et al.44, Pauleau et al.45, Cheung47]. This type of reactor was and still is the workhorse in IC fabs. Excellent films such as TEOS based oxides, thermal silicon-nitride and poly-silicon can be grown in such equipment. Hot wall tube reactors are suitable for these films because such materials stick very well to quartz tubes and are quite transparent to IR radiation of the heating elements. Thus neither particle nor temperature control is a problem. One other major advantage is that high throughputs are typically obtained. 

In the discussion below we limit ourselves to pure metal gates although alternatives have been proposed such as a tungsten/poly-silicon stack [Wong and Saraswat201]. It is helpful to keep the process flow as depicted in figure 8.1 in mind. 

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