Passivation etching

Slice preparation Passivation Etching Diffusions Metallization Die bonding Final seal Dendrite growth... 

Question by R. H. Anschutz, Pratt and Whitney Aircraft Were the effects of surface roughness or cleanliness or pretreatment, such as passivation, etching, heat treatment, etc., evaluated during this testing ... 

Step 11. If no additional metallisa tion layers are required, the substrate is covered with a passivation layer. If additional levels of metallisa tion are to be added to the stmcture, a blanket layer of a intermetal dielectric (IMD) is deposited. The resist is deposited, patterned (mask 5), and vias down to the Al in the first metal layer are etched. Steps 10 and 11 are repeated to form the second metal layer. 

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

Plating T anks. An electroless plating line consists of a series of lead-lined (for plastics etching) or plastic-lined tanks equipped with filters and heaters, separated by rinse tanks (24). Most metal tanks, except for passivated stainless steel used for electroless nickel, cannot be used to hold electroless plating baths because the metal initiates electroless plating onto itself. Tank linings must be stripped of metal deposits using acid at periodic intervals. 

Polyimides, both photodefinable and nonphotodefinable, are coming iato iacreased use. AppHcatioas iaclude planarizing iatedayer dielectrics oa iategrated circuits and for interconnects, passivation layers, thermal and mechanical stress buffers ia packagiag, alpha particle barriers oa memory devices, and ion implantation (qv) and dry etching masks. 

The passivity at pH values above about 1 5 is maintained in a great variety of solutions, including fruit juices, vinegar, sea-water, alkalis, and even ferric chloride. Hot caustic alkali solutions above about 10% attack the coating slowly, and the halogens etch it. 

Etch primers partially fulfil the roles of both pretreatment and primer. They contain phosphoric acid for surface passivation and are based on polyvinyl butyral ... 

The best protection is given by paint. An etch-primed paint scheme can be applied directly to the metal for other paints an inorganic treatment must be given to ensure good adhesion. Of the two classes of inorganic treatment, phosphate treatment has little protective value in itself, but chromate passivation gives appreciable protection and in mildly corrosive surroundings may be sufficient in itself. 

The determination of polarisation curves of metals by means of constant potential devices has contributed greatly to the knowledge of corrosion processes and passivity. In addition to the use of the potentiostat in studying a variety of mechanisms involved in corrosion and passivity, it has been applied to alloy development, since it is an important tool in the accelerated testing of corrosion resistance. Dissolution under controlled potentials can also be a precise method for metallographic etching or in studies of the selective corrosion of various phases. The technique can be used for establishing optimum conditions of anodic and cathodic protection. Two of the more recent papers have touched on limitations in its application and differences between potentiostatic tests and exposure to chemical solutions. ... 

These authors constructed Pourbaix diagrams for the MnTe, ZnTe, Cdi , Mn i Te, and Cdi cZn cTe systems and argued that the related analysis is an effective approach to determine conditions for selective etching, chemical polishing, passivation, and self-metallization of ZnTe, MnTe, and their solid solutions. 

The TFTs are made on transparent glass substrates, onto which gate electrodes are patterned. Typically, the gate electrode is made of chromium. This substrate is introduced in a PECVD reactor, in which silane and ammonia are used for plasma deposition of SiN as the gate material. After subsequent deposition of the a-Si H active layer and the heavily doped n-type a-Si H for the contacts, the devices are taken out of the reactor. Cr contacts are evaporated on top of the structure. The transistor channel is then defined by etching away the top metal and n-type a-Si H. Special care must be taken in that the etchant used for the n-type a-Si H also etches the intrinsic a-Si H. Finally the top passivation SiN, is deposited in a separate run. This passivation layer is needed to protect the TFT during additional processing steps. 

Jin and Atrens (1987) have elucidated the structure of the passive film formed on stainless steels during immersion in 0.1 M NaCl solution for various immersion times, employing XPS and ion etching techniques. The measured spectra consist of composite peaks produced by electrons of slightly different energy if the element is in several different chemical states. Peak deconvolution (which is a non-trivial problem) has to be conducted, and these authors used a manual procedure based on the actual individual peaks shapes and peak positions as recorded by Wagner et al. (1978). The procedure is illustrated in Figure 2.8 for iron. 

Figure 19. Schematic drawing of cross sections of two types of pits developing in pitting corrosion of passive metals (a) geometric pit (b) crystallographic or etch pit.

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