Transistor channel

The TFTs are made on transparent glass substrates, onto which gate electrodes are patterned. Typically, the gate electrode is made of chromium. This substrate is introduced in a PECVD reactor, in which silane and ammonia are used for plasma deposition of SiN as the gate material. After subsequent deposition of the a-Si H active layer and the heavily doped n-type a-Si H for the contacts, the devices are taken out of the reactor. Cr contacts are evaporated on top of the structure. The transistor channel is then defined by etching away the top metal and n-type a-Si H. Special care must be taken in that the etchant used for the n-type a-Si H also etches the intrinsic a-Si H. Finally the top passivation SiN, is deposited in a separate run. This passivation layer is needed to protect the TFT during additional processing steps. 

Hoffman, R. L. 2004. ZnO-channel thin-film transistors channel mobility. /. Appl. Phys. 95 5813-5819. 

Using impedance spectroscopy we measured transistors with solution processed pentacene as the semiconductor. Fabrication details are discussed in Section 13.3.1. We have made use of a ring-type transistor, in which the source electrode forms a closed ring around the transistor channel and the drain electrode, at which the current is monitored. Using this geometry, the measurements are insensitive to parasitic currents that may flow outside the transistor area [29]. 

FIGURE 20.10 Intel Corp. s schematic representation of a tri-gate transistor and an SEM image of a seven-leg tri-gate transistor. The use of three dimensions allows aerial scaling while increasing the width of transistor channel used for conduction (from Ref. 8). 

Figure 3. Two eTcamples of breakdown induced DBIE microstnictuies which are useful nanomarker for locating the breakdown spot. DBIE (a) near gate e e and (b) in transistor channel.

The surface of the pentacene film was examined by atomic force microscopy (AFM). It exhibits crystallites with a diameter of about 250 run in the transistor channel. On the gold surface of the drain and source contacts, the dimensions are twice the size as on silicon dioxide. In comparison with growth studies in [18] where the surface was pretreated by an adhesion promoter, the presented pentacene film consists of very small crystallites. 

Figure 18.11 AFM scan of a pentaeene film on a polyimide film as gate dielectric in the transistor channel of the introduced transistor. Below the hlack hne, one electrode of the drain and soruce contacts can he observed.

Here I, represents the drain current and ju, jUp the respective electron and hole mobility. C defines the area capacitance of the insulator. The channel geometry is defined by the channel width W and length L. The ambipolar range, described by Eq. (3), is only valid as long as both electrons and holes can be injected and further transported in the active layer of the transistor. However, in most cases the injection and/or the transport in the transistor channel are suppressed for one charge carrier type. In that case, the FET operates only in the unipolar and saturation range as described by Eqs. (1) and (2). 

As a matter of fact, the observed degradation in the device parameters occurs with the first indication of a metallic fraction in the Ca adsorbate. Even more, the device performance is significantly degraded as soon as the Ca characteristic Ca2p3/2 and Ca2pi/2 emission lines are clearly developed. This implies that the availability of metallic Ca at the dielectric interface, even in small quantities, has a negative effect on the electron transport along the dielectric-semiconductor interface. It is likely that the metallic fraction in the oxidized Ca layer disturbs or even fully screens the electric field in the transistor channel. 

In this proceedings report we focus on the investigation of some peculiar, though quite important aspects, such as the effect on the OTFT sensor response of the active layer thickness and morphology as well as of the transistor channel length. 

While it is simpler from a fabrication standpoint to deposit the same contact material for both the source and drain contacts (symmetric contacts), one may also consider choosing two different materials for each contact (asymmetric contacts). Based on energy band line-up considerations with the semiconductor HOMO and LUMO levels, depositing two different contact materials at either end of the transistor channel may facilitate more efficient hole and electron injection, respectively. At this point, it is unclear whether separately engineering distinct contacts for hole/elec-tron injection in ambipolar OFETs will prevail over opting for symmetric contacts. However, there will certainly be more reports on this exciting OFET subclass in the next few years. 

Figure 5.5.23 illustrates the electrical properties of a representative nanoscale laminated transistor (channel width of 20 [tm and channel length of 150 mn). The transistor exhibits a lower charge-carrier mobility and on/off current ratio compared to laminated micron-size transistors (channel width of 20 pm and channel lengths of 2.5 and 100 pm). Zaumseil and coworkers attributed the differences to contact resistances and short-channel effects [88]. Methods to lower contact resistance, which may include the clever use of monolayer chemistty and conductive polymers as electrodes, are being explored [87,88]. 

OTFT sensors have device structures and detection mechanisms different from those of CHEMFETs. In the case of OTET sensors, the analyte detection is performed employing a bottom gate device structure where the active layer is directly exposed to the analyte and acts as both transistor channel material and sensing membrane. 

One of the critical operating junctions in OFET devices is the source and drain contact to the channel. Any barrier between the contacts and the channel will appear in series and impede the flow of charge through the device. The source and drain electrode formation and structure can also influence the properties of the transistor channel itself. Crystal growth nucleated on the source and drain and the processes used to pattern the source and drain electrodes can have a significant effect on overall device performance. 

Fig. 6.7. Sschematic models foi C — V measurement of OFETs. (a) shows the connection made to take the characteristic Vos is set to OV and the capacitance is measured between the gate and the shorted source and drain electrodes. In accumulation (b) there are three major contributions to the total capacitance the channel capacitance C oxWL, the gate/source overlap capacitance Cos, and the gate/drain overlap capacitance C gd- In depletion (c), only the overlap capacitance is observed, there is no mobile charge in the channel to contribute to a channel capacitance. The transistor channel is really a distributed RC structure and the lumped R shown is only schematic.

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