Parallel load

However, the power factor of the current drawn from the supply will only improve if the power factor of the generated current is less than that of the parallel loads, since the active power drawn from the supply will also be reduced by the amount of actual power generated. In each case increasing the excitation so that the power factor of the current drawn from the supply can improve to unity or become leading can increase the reactive current produced by the synchronous machine within the capabilities of the machine. In this case, the installation becomes a net exporter of lagging reactive current to the supply. Figure 16.8 illustrates these two cases. 

It can be shown from Figure 11 and Equation 1 that the rise time of the signal will be controlled by the RC time constant of the circuit loading the pyroelectric current generator. The simplest case is where the heat flow into the pyroelectric is one dimensional as shown in Figure 12. Then the signal across the parallel load resistor of the pyroelect-ic element is... 

The interconnect of the Samson Box was quite novel, ft was called sum memory and was implemented by parallel loading counters and then writing the result back into RAM. The connection memory acted as a double-buffered multiport memory by dividing the memory into quadrants as shown in figure 5.5. 

One is the secondary- coolant reduction test by partial secondary loss of coolant flow in order to simulate the load change of the nuclear heat utilization system. This test will demonstrate that the both of negative reactivity feedback effect and the reactor power control system brings the reactor power safely to a stable level without a reactor scram, and that the temperature transient of the reactor core is slow in a decrease of the secondary coolant flow rate. The test will be perfonned at a rated operation and parallel-loaded operation mode. The maximum reactor power during the test will limit within 30 MW (100%). In this test, the rotation rate of the secondary helium circulator will be changed to simulate a temperature transient of the heat utilisation system in addition to cutting off the reactor-inlet temperature control system. This test will be performed under anticipated transients without reactor scram (ATWS). 

Convert the parallel load into a series load of / oii + 7- ou-The formulae for this conversion are -... 

Plateout distributions in die parallel loaded operation at rated power operation, i.e. 850 °C of outlet coolant temperature, are shown in Fig, 5. It is predicted that both l and Cs plateout mainly on die heat transfer tubes of PWC where temperature is relatively low in the primary cooling system of the HTTR. On the other hand, there are very small amounts of plateout FPs on the inner pipe of co-axial double pipe where temperature is very high and therefore, desorption rate is large by its high lattice excitation frequency. From the calculation results, it is predicted that... 

FIGURE 10.63 Inverter types (a) parallel loaded or parallel resonant inverter, (b) series-parallel loaded (or LCC type) resonant inverter. 

FIGURE 10.65 Phaser circuits for nth harmonic (a) series-loaded inverter, (b) parallel-loaded inverter, (c) series-parallel resonant inverter. Note (1) Vabo and are the nth harmonic phasors of voltage vab and the output voltage... 

Figure 10.66 shows the plots of inverter gains vs. frequency ratio F obtained using the equations derived previously. It can be observed that the frequency variation required for load regulation is very wide for a series-loaded inverter, whereas it is very narrow for a parallel-loaded resonant inverter. But the inverter switch peak current decreases with the load current for a series-loaded inverter, whereas it does not decrease with the load current in the case of a parallel-loaded inverter. The series-parallel resonant inverter combines the advantages of series-loaded and parallel-loaded resonant inverters. Also, with a proper selection of Cj / Cp ratio, a near sine-wave output waveform which is almost load independent can be obtained. 

This last concept has been extended to what is known as capillary array electrophoresis (CAE) (Huang et al., 1992 Kheterpal and Mathies, 1999), wherein there may be as many as 96 capillaries in parallel in instmments currently available (Zubritsky, 2002). This increases the throughput drastically. Such devices were the workhorse of the human genome analysis. Scaling up to 1000 capillaries has also been reported (Kheterpal and Mathies, 1999). Capillary array electrophoresis enables easy and parallel loading of multiple samples as well as rapid and parallel separation and detection using appropriate detection techniques. 

This section presents a more practical design example, employing some of the language constructs and features illustrated in this chapter. A behav-iotural design style has been adopted for this circuit, an up-down counter with a parallel loading facility. The counter is only 3 bits wide so that its characteristics can be observed without the needless repetition of logic. 

TEMPCOUNT = COUNTVAU - initialize the variable if LOAD= 0 then - parallel load the counter TEMPCOUNT = LOADVAU elsif ENABLE= 0 then - counter is enabled... 

The other correction term, 6u2, is calculated only for the selected chain, which means only once. This means that the calculation of 6u2 can be divided among processors. If the amount of CPU time required to calculate 6u2 is large and this calculation cannot be parallelized, load-imbalance occurs. When 6ui = 0 and 6u2 0, the acceptance probability will not be equal to one in the limit of g —> 00. 

The start signal line at the output of A14d is also used to keep the A35 and A34 time generator counters reset while the line is at logic 1 (counting not started) simultaneously, it also keeps the parallel load of the down counters enabled. 

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