Inference flip flop

How is a flip-flop inferred It depends on the modeling style being followed and the context under which a variable is assigned a value. This... 

Figure 2-47 Falling-edge-triggered flip-flops inferred.

Figure 2-48 Flip-flops inferred from a variable assigned under clock control.

A task call can represent either combinational logic or sequential logic depending on the context under which the task call occurs. By this, we mean that the output parameters of a task call may imply memory depending on the context in which they are assigned. For example, if a task call occurs in a clocked always statement (always statement with a clock event), then an output parameter in a task call may be synthesized as a flip-flop this is determined by using the flip-flop inference rales. A synthesis system implements a task call by expanding the task call in-line with the rest of the code in effect, no separate hierarchy for the task call is maintained. 

It is important to understand the flip-flop inference rules of a synthesis tool. These rules may vary from one synthesis tool to another. If the inference rules are not followed, a synthesized netlist may have many more flip-flops than are really necessary. Here is a case in point. 

The architecture BADJK, uses two signals to store the present states of the flip flops inverted and non-inverted outputs, SBAR and S. The Case statement inside the S3mchronous section is used to determine the new state of S and assign its value. The value of S is then passed on to SBAR at the end of the Case statement. Unfortunately, the new state is not registered on the flip flop inferred for S until the end of the process so the SBAR will be assigned the old state of S. If this is not bad enough, because SBAR is assigned inside the synchronous section, it also infers another flip flop ... 

At the higher kinetic energy, of course the same forces act upon the molecule. But now the molecule is too fast to become significantly reoriented before it hits the repulsive wall of the potential at t = 50 fs. When the molecule reaches the surface in the tilted configuration, it starts quickly rotating in a flip-flop motion until the other end hits the surface. The molecule is then scattered back into the gas phase rotationally excited (which can not been infered from the panel at t = 300 fs). 

A flip-flop is inferred from a variable when it is assigned a value in a special form of always statement. This always statement is of the form ... 

The assignment to output Zee occurs only at the falling edge of the clock. Variable Zee is inferred to be a falling-edge-triggered flip-flop. The flip-flop shown in the figure has a data-select, that is, the input Control selects either A or B as the data for the flip-flop. 

Hip-flop inference rule is simple If a variable is assigned a value under the control of a clock edge, a flip-flop is generated an exception to this rule is when a variable is assigned and used only locally within an always statement as an intermediate variable. 

In this example, NextState is assigned a value only if there is a rising edge on Clk. Thus, four rising-edge-triggered flip-flops (needed to store values 0 through 15) are inferred for reg NextState. 

If a falling-edge-triggered flip-flop are to be inferred, then the clock edge event posedge Clk needs to be replaced by ... 

Integer variables assigned under the control of a clock edge are also inferred as flip-flops. Here is an example where an integer variable is assigned under clock control. Four flip-flops are inferred for the variable IntState) the other high-order bits of the variable are optimized away (since they are not used). 

What happens in the above case if we switch the order of the statements around In this case, since the value of Temp is used before its assignment, its value needs to be retained across multiple clock cycles, thereby inferring flip-flops for Temp. Temp models the internal state of the always statement. This is shown in the following example, where Temp is used before its assignment. 

In this case, falling-edge-triggered flip-flops are inferred for variable Temp, in addition to those for NextState. 

Variables (reg and integer types) declared locally within an always statement do not infer flip-flops. This may potentially lead to a functional mismatch between the Verilog HDL model and the synthesized netlist. Here is an example of a locally declared variable Temp that does not get inferred as a flip-flop. 

Figure 2-49 A variable used before its definition is inferred as a flip-flop.

No flip-flops are inferred for Temp since it is locally declared within the always statement and a value is assigned to the variable and used immediately in the same clock edge. Flip-flops are inferred for NextState (as this... 

However, a potential for mismatch exists between the design model and its synthesized netlist if the order of the above statements are reversed. This is because no flip-flops are inferred for locally declared variables. Here is such a model. 

The synthesized netlist is the same as in Figure 2-48. Notice that on every clock edge, NextState always get the value of Temp assigned in the previous clock cycle, but not so in the synthesized netlist. The recommendation here is to avoid using locally declared variables in this fashion. Hopefully a synthesis tool will issue a warning if no flip-flops are inferred for Temp. 

So far we have talked about synthesizing simple D-type flip-flops. What if we wanted to infer a flip-flop with asynchronous preset and clear To generate such a flip-flop, a special form of if statement has to be used. This is best shown with an example template. 

Here is another example of inferring a flip-flop with asynchronous preset and clear. 

From this example, it appears that all the inputs to NextState, the value 12, the value 5, and the variable CurrentState, should be multiplexed using appropriate select lines into the D-input of the inferred flip-flops for Next-State. This is exactly what occurs as shown in the synthesized netlist in Figure 2-55. So then, how can we infer flip-flops with synchronous preset and clear A synthesis system may provide a solution for this by providing a special option for directing the synthesis system to generate a synchronous preset clear flip-flop. 

In this case, the assignment to FCR must complete first before assignment 2 is done. Thus to mimic the language semantics, the right-hand-side expression of assignment 1 must be used to form the logic for the data for Claim. This is shown in the synthesized netlist. In addition, no flip-flop is inferred for FCR since its value is assigned and then used the value of FCR does not have to be saved between different iterations of the always statement. 

If a variable is assigned a value z in an always statement in which the variable is also inferred as a flip-flop, then it becomes necessary to save the enabling logic of the three-state also in a flip-flop. Here is the same example as above except that the always statement is controlled by a clock event. 

Sequential logic elements, that is, flip-flops and latches, can be inferred by writing statements within an always statement using styles described in Chapter 2. It is best not to synthesize a memory as a two-dimensional array of flip-flops because this is an inefficient way to implement a memory. The best way to create a memory is to instantiate a predefined memory block using a module instantiation statement. 

When this model is synthesized, three flip-flops are inferred two to hold the value of the machine state (MooreState) and one for the output Z. States are encoded using sequential state assignment. 

Two flip-flops are inferred to hold the value of the variable MealyState with the specified state assignment. The default branch in the case statement can be avoided by specifying the case statement as full case , as shown next. 

Synthesis infers four flip-flops for this model, three for variable Previous and one for SeqFound. However, optimization reveals that one of the flip-flops for Previous is not necessary and hence it is removed. In this model, the output is latched since it is assigned a value under the control of a clock edge. If a latched output is not desired, then the assignment to SeqFound must be done outside the always statement. Such a module is shown next. 

In this module, the output SeqFound is not latched. Synthesis infers three flip-flops for variable Previous note that in this case, all the bits of Previous have to be latched. 

When synthesized, flip-flops are inferred for InLatch, Result, Exponent and Done. 

Here is the behavioral model for the transmitter block TX. This model is a synthesizable model. Rising-edge-triggered flip-flops are inferred for variables TBR, TR, TRE, TBRE, DOUT, CBTT and PA this is because these variables are assigned values under the control of clock CK. 

Here is the behavioral model for the receiver block RX. This model is also synthesizable. Flip-flops are inferred for variables START, CBIT, CSAM, DI, PI, SR, DR, DOUT, PERR, FERR and OERR. 

Here is a synthesizable model for the divider block DIV. This circuit produces a pulse every sixteen clock cycles. If input TESTN is 0, ENA is set to a 1. Variable COUNT is inferred as flip-flops. 

HDL code can be behavioral or RTL. In the synthesis domain, the latter is usually considered to be the synthesizable form of HDL code. Since the focus of this book is on logic synthesis, all examples discussed are in synthesizable RTL code. As a preliminary introduction to HDL coding and synthesis let us consider the following simple examples. Four examples of HDL code which infer on synthesis a D-flip flop, a latch, an AND gate, and a multiplexer (referred to as mux throughout this book) respectively are discussed. 

Example 7.1 Inferring Flip-Flops with Clock Enable... 

A flip flop or any storage element is inferred inside a Process statement. The template that indicates a sec]uential logic section is formed from either a Wait statement or an If statement. 

A signal assignment inside the process shown below would infer to the synthesizer that the signal should be the output of a flip flop that is triggered by the signal CLK. 

It is also possible to use an If statement to infer flip flops. In this case the statement... 

The most common and definitely the best way of achieving this is to attach an external asynchronous or synchronous reset signal to each and every storage element in the circuit. When an external initialization signal is specified, the compiler will select an appropriate component from the library (if the elements are inferred). For example, if a flip flop is required to be initialized to V, the selected element will possess an input for a preset signal. A variety of designs based on this form of initialization are given in the examples in this chapter. 

Figure S3 Inferring a flip flop with a synchronous preset and dear...

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