Case statement

A case statement behaves like a nested if statement, that is, the value of the case expression (Op) is checked with the first case item (ADD), if it does not match, the second case item (SUB) is checked and so on. The equivalent i f statement for the above case statement is shown next. 

Figure 2-30 Logic generated from a case statement.

A latch may be inferred for a variable assigned in a case statement, just like in an if statement. If a variable is not assigned a value in all possible executions of the always statement, such as when a variable is assigned a value in only some branches of a case statement, a latch is inferred for that variable. See the following example. 

Figure 2-33 Latch inferred for a variable in a case statement.

A synthesis tool on encountering such a directive on a case statement understands that all possible values (that can occur in the design) of the case expression have been listed and no other values are possible. Consequently, a variable assigned in all branches of the case statement will never infer a latch. Here is the case statement in the NextStateLogic module with the directive specified. 

An alternative way to avoid latches in the above example is to specify a default branch in the case statement or to make a default assignment to all variables assigned in a case statement (in this example, NextToggle), prior to the case statement. Here is an example that uses a default branch to avoid inferring latches. 

Verilog HDL semantics of a case statement specifies a priority order in which a case branch is selected. The case expression is checked with the first case item, if it is not the same, the next case item is checked, if not the same, the next case item is checked, and so on. A priority order of case item checking is implied by the case statement. Additionally, in Verilog HDL, it is possible for two or more case item values to be the same or there may be overlapping case item values such as in casex and casez statements however, because of the priority order, only the first one in the listed sequence of case items is selected. 

To apply the strict semantics of a case statement in synthesis to hardware, a nested if-like structure (priority logic if this do this, else if this do this, else. ..) is synthesized. Here is an example of a case statement. 

The equivalent behavior of the case statement is expressed in the following if statement. 

What if the designer knows that all case item values are mutually exclusive In such a case, a decoder can be synthesized for a case statement control (the case expression is checked for all possible values of the case item values in parallel) instead of the priority logic (which could potentially be nested deep depending on the number of branches in the case statement). 

The information that all case item values are mutually exclusive needs to be passed to the synthesis tool. This is done by using a synthesis directive called parallel case. When such a directive is attached to a case statement, a synthesis tool interprets the case statement as if all case items are mutually exclusive. Since the synthesis directive appears as a comment in the Verilog HDL model, it has no effect on the language semantics of the model. This implies that no priority logic is synthesized for the case statement control instead decoding logic is used. Here is the case statement with the parallel case directive. 

The equivalent synthesis interpretation for the case statement is as follows (with only one if condition guaranteed to be true). 

It is necessary to specify the full case synthesis directive, otherwise latches are inferred for Address. Alternatively, an initial assignment to Address before the case statement can also be made to avoid latches no synthesis directive is then necessary. This is shown in the following always statement. 

Figure 2-38 Priority encoder using case statement, case (l bl)...

A variable declared locally within an always statement is also inferred as a latch if it is incompletely assigned in a conditional statement (if statement or case statement). This is shown in the following module. 

When value x is used in a case item of a case statement (not casex, casez), the branch corresponding to that case item is considered never to execute for synthesis purposes. 

The value z is used to generate a three-state gate. The value z can be assigned to a variable in an assignment statement however for synthesis, such an assignment must occur under the control of a condition, either in an if statement, or in a case statement. Here is an example. 

In a Moore finite state machine, the output of the circuit is dependent only on the state of the machine and not on its inputs. This is described i pictorially in Figure 3-5. Since the outputs are dependent only on the j state, a good way to describe a Moore machine is to use an always state- j ment with a case statement. The case statement is used to switch between j the various states and the output logic for each state is described in the appropriate branch. The always statement can have the clock event in its] event list to indicate that it is a clocked always statement. This models the] condition of a finite state machine going from state to state synchronously j on every clock edge. The machine state itself is modeled using a reg vari-] able (a variable of reg data type). 

Two flip-flops are inferred to hold the value of the variable MealyState with the specified state assignment. The default branch in the case statement can be avoided by specifying the case statement as full case , as shown next. 

Another option is to declare parameters and use these in the case statement. 

II Assume that the second assignment is executed every // time the first statement is executed. Note that this // assumption may not be true if either of the statements //is inside an if statement or a case statement. 

Common factoring is the extraction of common subexpressions in mutually-exclusive branches of an i f statement or a case statement. Here is an example. 

Here the intention appears to be to store the value of PresentState in a flip-flop (rising-edge-triggered). After synthesis, not only is there a flip-flop for PresentState, there are also four flip-flops for Zout. This is because Zout is assigned under the control of a clock. It may or may not be the intention to generate flip-flops for Zout. If not, then a case statement needs to be written in a separate always statement in which Zout is assigned, this... 

A variable that does not have a value assigned in all branches of a case statement or an if statement can lead to a latch being built. This is because in Verilog HDL, a reg variable (assigned within an always statement) infers memory, and thus if the variable is not assigned a value in all branches of a conditional statement, the value needs to be saved in memory. Here is an example. 

There is no correlation between the gates produced and the number of lines of Verilog HDL code. A 2500-gate circuit could have been synthesized from a 10-line Verilog HDL code (may have a for-loop and/or vectors) or from 10,000 lines of Verilog HDL code (maybe from a large case statement with simple assignments). 

The full case directive tells the synthesis tool that all possible values that can possibly occur in CurrentState have been listed and the value of Next-State is a don t-care for all other cases, and therefore, the synthesis tool should not generate latches for NextState. However this may not be true in simulation. It could happen that CurrentState for some reason, gets a value of 2 b00. In such a case, the case statement simulates as if NextState value is saved, but in the synthesized netlist, the value of NextState may not be saved. 

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