Flip flop rising edge triggered

In this example, NextState is assigned a value only if there is a rising edge on Clk. Thus, four rising-edge-triggered flip-flops (needed to store values 0 through 15) are inferred for reg NextState. 

Here is the behavioral model for the transmitter block TX. This model is a synthesizable model. Rising-edge-triggered flip-flops are inferred for variables TBR, TR, TRE, TBRE, DOUT, CBTT and PA this is because these variables are assigned values under the control of clock CK. 

Startpoint f reg (rising edge-triggered flip-flop clocked by dk)... 

The Walt statement will be discussed in the next section, but this statement means.. when the signal CLK changes and that change is from 0 to 1, clock the function of the flip flop. This is a rising edge-triggered flip... 

Here the intention appears to be to store the value of PresentState in a flip-flop (rising-edge-triggered). After synthesis, not only is there a flip-flop for PresentState, there are also four flip-flops for Zout. This is because Zout is assigned under the control of a clock. It may or may not be the intention to generate flip-flops for Zout. If not, then a case statement needs to be written in a separate always statement in which Zout is assigned, this... 

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