Synchronous section

Grape maturation at a vineyard, in a parcel or even on the same grape cluster, is never absolutely synchronous (Section 10.4.1). As soon as a berry approaches maturity, it is contaminated by conidia... 

Unlike the Wait statement, the If does not have to be the first statement in the process. This allows both a synchronous section and combinational logic - a combinational section - to exist in the same process. The example below illustrates this (and assumes that all the signals have been declared in the surrounding architecture). 

Although only one synchronous section is shown here, any number of them could be described in a single process. In this example, the signal S is assigned a value inside the synchronous section whereas A and C are assigned values outside in the combinational part. The compiler will there-... 

A signal assigned in one synchronous section cannot be assigned again in any other synchronous section, either in the same or a different Process statement. 

A synchronous section cannot be nested inside another synchronous section. 

This section has illustrated the important part that the Process statement plays in the design of sequential logic. In Chapter 4, its function in combinational design was also shown. It is good design practice to separate combinational and synchronous sections by using different processes. Box 5.1 offers some guidelines on how to use the process statement and illustrates its syntax. 

A signal assigned inside a synchronous section is synthesized as a flip flop. If it is assigned inside a combinational section it will be synthesized as a signal on a wire. 

Section 5.1.2 illustrated how a block of combinational logic can form part of a process that infers a flip flop. This block does not need to be associated with the logic in the synchronous section(s) of the process, although if it is not then it should usually be placed in a separate process. Generally, the combinational section should be used to implement any logic that does not need to be located within the synchronous section. Using this approach, synchronous blocks with minimum clock-to-output propagation delays should result. 

ASYNC JFI illustrates an architecture with completely separate combinational and synchronous sections. Alternatively ASYNCJK shows how the synchronous section can hang off the combinational section. In this example, note that the clock expression is on the last branch of the If statement. It would be an error if this statement was followed by another Elsif or an Else statement. 

In ASYNC IF I, if INIT is low then the register will be initialized to 1000, independent of the state of the clock. It will be held in this state while INIT remains low, regardless of the number of dock pulses received. The synchronous and asynchronous sections should not drive REG at the same time. To ensure this does not happen, a conditional statement within the synchronous section determines the state of INU before the bits in the register are shifted. This will require additional logic for its implementation. 

Any number of synchronous sections may appear in a single process and any number of processes within Ae architecture may contain s)mdiionous sections. 

Asynchronous initialization combined with the synchronous section... 

Box 5.7 How to create a synchronous section with a Wait statement... 

A process that contains a Walt statement is a template for a fully synchronous section of an architecture. The clarity of the code is often better than when If statements are used. The following syntax is required ... 

Assign the new value of ihe counter stored in the variable back to the signal. The signal therefore infers sequential logic as it is assigned inside a synchronous section. 

The architecture BAD I assigns the flip flops output values, Q and QBAR, inside the process. The rules for inferring flip flops state that any signal assigned inside a synchronous section becomes the output of a flip flop. This description therefore infers two flip flops as shown in Figure 5.32. 

The architecture BADJK, uses two signals to store the present states of the flip flops inverted and non-inverted outputs, SBAR and S. The Case statement inside the S3mchronous section is used to determine the new state of S and assign its value. The value of S is then passed on to SBAR at the end of the Case statement. Unfortunately, the new state is not registered on the flip flop inferred for S until the end of the process so the SBAR will be assigned the old state of S. If this is not bad enough, because SBAR is assigned inside the synchronous section, it also infers another flip flop ... 

If the signal (or variable) infers a storage element (in a synchronous section elsewhere) then the logic of the assignment becomes part of the asynchronous combinational input logic to the storage element. 

The rules for the creation of synchronous sections with both Wait and If statements were fully explained in Chapter 5. The Dos and Donats section... 

We overview in this chapter the hardware modeling language and synthesis flow in Hercules and Hebe. Section 2.1 describes the modeling of hardware behavior using HardwareC [KM90a]. HaidwaieC supports constraint specification and ext ual synchronizations. Section 2.2 presents a brief overview of the ovoall synthesis flow in Hercules and Hebe. 

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