Logic synthesis

With the s)mthesis route, the process of mapping into particular integrated circuit technologies is automated. The synthesis process flierefore both increases productivity (through automation) and reduces flexibility (by restricting Ae choice of technology). 

So far this chapter has mentioned logic synthesis without precisely defining it. The general view of logic s)mthesis software is of a CAD tool that 

1 It is possible to specify behaviour fliat is impossible to implement. For example, two numbers are added after exactly 3.2 ns. It is dearly impossible to meet these conditions, as the time delay will depend on tedmol-ogy, circuit design, what numbers are being added, the number of bits involved, the temperature and power supply, to name a few parameters. 

2 It is possible to write VHDL code that the synthesizer cannot cope with. For example, relatively few synthesis tools can support division operations. Furthermore, some VHDL design styles are impossible for die synthesizer to analyse successfully. As time progresses, research into these issues means that the capabilities of the software ate continuously improving, but nonetheless substantia] limitations exist. It is a major aim of this book to communicate techniques that enable the writing of VHDL code that can readily be processed by logic synthesis software. 

These models include transport wire delays and pin-to-pin delays in the delay model. In addition to warning messages, the Simulator can schedule X output values for timing constraint violations and circuit hazards. One can use the FTGS library for fast, sign-off-quality timing verification. 

Note The encrypted file works only with the Synopsys VHDL System Simulator (VSS). 

If one has the source library file (.lib file), one can write out VHDL models using the following dc shell command. One can control the type of VHDL model written out (that is, UDSM, FTBM, FTSM or FTGS) by setting the dc shell variable vhdilib.architecture. 

Behavioral simulation and examples of VHDL simulation models are provided in Chapter 3. 

The logic synthesis process consists of two steps - translation and optimization. Translation involves transforming a HDL (RTL) description to gates, while optimization involves selecting the optimal combination of ASIC technology library cells to achieve the required functionality. 

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In many respects, this is the kernel of this book. For years it has not been too clear how one could consistently account for the wide variety of transition-metal chemistry in a way that does not conflict with the equally varied phenomena of spectroscopy and magnetochemistry that are so well rationalized by ligand-field theory. There is a tendency - psychologically quite natural, no doubt - for those interested in synthetic and mainstream chemistry not to look too closely at theory and physical properties, and, of course, vice versa. However, there has always been the need, surely, to build a logical synthesis of, or bridge between, these two aspects of the same subject. We hope that our presentation in this book goes some way towards providing that overview. 

Nonetheless, Kolbe achieved his goal of proving that vitalism was untenable by designing and executing a logical synthesis of a natural organic substance from the elements. 

The logical synthesis of HNCC presents a major problem. The transition metals exhibit a complex array of bonding modes and a far more extensive range of coordination numbers than their main group counterparts, which have dependable valences and, in the main, strongly directional bonds. This, combined with the relative similarities of M—M, M—CO, and M—H bond energies (454), makes the designed synthesis of HNCC difficult. 

R. K. Ranjan, A. Aziz, R. K. Brayton, B. Plessier, and C. Pixley. Efficient BDD Algorithms for FSM Synthesis and Verification. In IWLS 95 IEEE Interna-tional Workshop on Logic Synthesis, Lake Tahoe, CA, USA, May 1995. 

U. Kebschull, E. Schubert, and W. Rosenstiel. Multilevel logic synthesis based on functional decision diagrams. European Conference on Design Automation, pages 43-47,1992. 

Apart from the integration of Amical with an existing logic synthesis tool, future work includes the generation of other styles of architecture (e.g., mux-based) and to extend the interaction with Amical in order to allow microarchitecture simulation [10]. 

G. De Micheli. Synthesis of control systems. In G. De Micheli, A. Sangiovanni-Vincentelli, and P. Antognetti, editors, Design systems for VLSI Circuits Logic Synthesis and Silicon Compilation Martinus Nijhoff, pages 327-364, 1987. 

K. Ranerup and J. Madsen. Comparision of logic synthesis methods in control unit architecture synthesis. Technical report, Esprit project BRA 3281, CD/m30/El-E2/l. 

Fig. 2.1 Major stages of physical design include floorplanning and logic synthesis, followed by physical synthesis beginning with global placement, and finishing with routing and design for manufacturing. Physical synthesis can be iterated with modified parameters to improve the result, however, this flow does not always converge to an acceptable solution...

In practice, it is difficult to evaluate the exact effect of high-level transformations. At this point in the synthesis process, measures such as size, power, and delay are only estimates, as they can be evaluated exactly only when the real hardware is generated. For example, what may seem to be a critical path with respect to timing may turn out to be faster than other paths after logic synthesis. In contrast, a path that appears to be fast at a high level may turn out to be critical l cause of unexpected wire delays. Thus, high-level transformations must be applied with care, and often only the designer can decide which transformations to apply. 

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