Functional mismatches

Any kind of delay, delay control or intra-statement delay, specified in a procedural assignment (blocking or non-blocking) is ignored by a synthesis system. This can potentially lead to a functional mismatch between the design model and its synthesized netlist. 

A word of caution. The synthesis directive, parallel case, can potentially cause a functional mismatch between the design model and the synthesized netlist Chapter 5 elaborates on this further. 

Variables (reg and integer types) declared locally within an always statement do not infer flip-flops. This may potentially lead to a functional mismatch between the Verilog HDL model and the synthesized netlist. Here is an example of a locally declared variable Temp that does not get inferred as a flip-flop. 

Verilog HDL has two non-logical values x (unknown) and z (high-impedance). In this section, we specify the domain under which these values can be used for synthesis. Use caution when using these values in a synthesis model as they can potentially cause a functional mismatch between the design model and the synthesized netlist. 

Thus a functional mismatch may occur a synthesis tool may report a warning in such a case. Avoid using x in a case item of a case statement (not casex, casez). 

In this chapter, we assume that this verification step is performed using simulation which verifies the functionality between the design model and its synthesized netlist. We illustrate some cases of functional mismatches between the design model and its synthesized netlist that might possibly occur, describe their cause, and provide recommendations for avoiding them. 

Another approach is to write a test bench a test bench is a model written in Verilog HDL that applies stimulus, compares the output responses, and reports any functional mismatches. Figure 5-3 shows such a scenario. A test bench for a full-adder is shown next. The stimulus is read from a vector file Inputs.vec its contents are of the form ... 

Recommendation To avoid delays in a design model from causing functional mismatches, the maximum delay in the model must be comput-... 

There are no latches for DebugX and Bdy. However language semantics indicate that Bdy needs to be saved. A synthesis system may not produce a latch it may generate a warning about the variable being used before its assignment and that there is a potential for a functional mismatch. 

Quite often, a synthesis system ignores the event list of an always statement during synthesis. This can lead to functional mismatches if proper care is not taken in modeling. Here is a simple example. 

Here is another example of an always statement with an incomplete event list that may cause functional mismatches. 

The variable Pbus is not in the event list of the always statement. However in the synthesized netlist, any changes on Pbus will propagate into Treg if the if condition is false. This is not consistent with the design model semantics and thus a functional mismatch occurs. 

The two synthesis directives we have seen so far, full case and parallel case, can potentially cause functional mismatches to occur between the design model and the synthesized netlist. The problem is that these directives are recognized only by a synthesis tool and not by a simulation tool. In either of the cases, if the designer is not careful in specifying the directive, mismatches can occur. 

When synthesizing an asynchronous preset clear flip-flop, the recommendation is to assign only constant values under the asynchronous conditions. If a variable is asynchronously read, there is a potential for a functional mismatch to occur. Here is an example. 

In this section, we explain why this recommendation is important to be followed else there is a risk of getting functional mismatches. 

A potential barrier, referred to as the Schottky barrier (SB), develops due to differences in the work fnnction between the semiconducting SWNTs and metal S-D the magnitude of this barrier is directly related to the work function mismatch between the semiconductor and metal electrodes. When a constant potential is applied... 

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