Sequential logic

A good practice is to include all variables read in the always statement in the event list this is true only when modeling combinational logic. When modeling sequential logic, a different kind of event list is required this is described later. 

Figure 2-45 Sequential logic synthesized using a special always statement.

A task call can represent either combinational logic or sequential logic depending on the context under which the task call occurs. By this, we mean that the output parameters of a task call may imply memory depending on the context in which they are assigned. For example, if a task call occurs in a clocked always statement (always statement with a clock event), then an output parameter in a task call may be synthesized as a flip-flop this is determined by using the flip-flop inference rales. A synthesis system implements a task call by expanding the task call in-line with the rest of the code in effect, no separate hierarchy for the task call is maintained. 

Sequential logic and combinational logic can be synthesized from a Verilog HDL description. There are two main styles for describing combinational logic ... 

Sequential logic elements, that is, flip-flops and latches, can be inferred by writing statements within an always statement using styles described in Chapter 2. It is best not to synthesize a memory as a two-dimensional array of flip-flops because this is an inefficient way to implement a memory. The best way to create a memory is to instantiate a predefined memory block using a module instantiation statement. 

Here is an example of a Mealy finite state machine. Variable MealyState holds the machine state, while NextState is used to pass information from the combinational logic always statement to the sequential logic always statement. Input Reset asynchronously resets the state to STO. 

Let us first consider what happens if blocking assignments are exclusively used for modeling sequential logic. Consider the following two always statements. 

A word web is the perfect graphic organizer for an essay that asks you to describe something. After brainstorming aii the detaiis you can, search for patterns or groupings to heip you organize further so that you can write a sequentially logical essay. 

The Deductive Discoverer. This individual designs or discovers molecules with unusual or interesting biomedical properties by developing a sequentially logical rationale, founded on a solid base of data. In... 

When propagated, the pulse hits the sequential latch window on the sequential logic to the right, which registers the incorrect value 0 , instead of a 1 . Such effects may be masked by the circuit, as discussed in the following subsections. 

The control path is defined as the decision logic of a processor. It is responsible for calculating the next instmction to be fetched and setting the internal flags, such as to command the ALU to sum or subtract, and a branch to be taken or not. The control path is mostly combinational, but since it has to cross the pipeline stages, also has sequential logic. The main difference between the control path and the data path is that an error in the control path will most likely lead to control flow errors, such as a branch being taken, when it should not have. Such control flow errors may cause an erroneous result in the end of the computation or even an infinite loop. 

In addition, effort has been spent on formal verification itself, especially regarding timing issues for control-flow-dominated systems. A study of propositional temporal logic has shown its feasibility to verify correctness of sequential logic circuits, CMOS transistor circuits, and finite state machine diagrams against each other [16]. This work has been received with great interest in the worldwide research community, since verifications were done that previously seemed untractable. It has been applied in the context of performance-driven controller synthesis, as described in chapter 10. 

---