Asynchronous preset

When synthesizing an asynchronous preset clear flip-flop, the recommendation is to assign only constant values under the asynchronous conditions. If a variable is asynchronously read, there is a potential for a functional mismatch to occur. Here is an example. 

QuickBus = LoadData // Asynchounous data assign, else 

Two flip-flops with asynchronous preset and clear are synthesized for the variable QuickBus. The variable LoadData is connected to the preset clear inputs of the flip-flops through other logic. When PreLoad is active (is 0) and LoadData changes, the outputs of the flip-flops are immediately affected because of the asynchronous data change. However in the design model, any change on LoadData has no effect on the output QuickBus. Thus there is a mismatch. 

Recommendation Avoid asynchronously reading a variable and assigning it to a flip-flop else ensure that there are no changes on asynchronous data when the asynchronous conditions are active. 

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For the above example, a synthesis tool may alternately not generate a latch with asynchronous preset and clear, but direct the preset clear logic into the D-input of a simple latch. This is shown in the synthesized netlist that appears in Figure 2-43. 

Figure 2-42 Latch with asynchronous preset and clear.

So far we have talked about synthesizing simple D-type flip-flops. What if we wanted to infer a flip-flop with asynchronous preset and clear To generate such a flip-flop, a special form of if statement has to be used. This is best shown with an example template. 

Since NextState is assigned a value under the control of a clock edge (Stmt C) and it is also assigned asynchronously (Stmt A and B), a falling-edge-triggered flip-flop with asynchronous preset and clear is synthesized. This is shown in Figure 2-53. Note that four flip-flops are required. The first flip-flop (the leftmost bit of NextState) has both asynchronous preset and clear terminals since it needs to be preset on Reset and cleared on Set. Similarly, the fourth flip-flop has both asynchronous preset and clear terminals since it needs to be preset on Set and cleared on Reset. The... 

Positive-level sense, positive asynchronous // preset, static D-type FF (latch). endmodule... 

II Negative edge-triggered, negative asynchronous // clear, positive asynchronous preset, static // D-type FF. endmodule... 

A structural style architecture can be used to model sequential circuits. The storage elements used in a sequential circuit are edge-triggered latches - flip flops - or level-triggered latches - transparent latches. These can be instantiated from libraries provided by the synthesis tool or technology vendor. This can limit the flexibility of an implementation as not all vendor technologies will support all types of storage elements. Elements such as flip flops with asynchronous preset and clear inputs, for example, may be omitted from a library. 

Restrictions on the content of clock statements. It is far too easy to create storage elements that require components which may it may not be possible to synthesize (e.g. a device with bodi a synchronous dear and asynchronous preset) using a particular library. (Qiapter 5 showed how a number of different D-types could be inferred.)... 

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