Deposition, silicon nitride layer

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The main goal of another microhotplate design was the replacement of all CMOS-metal elements within the heated area by materials featuring a better temperature stability. This was accomplished by introducing a novel polysilicon heater layout and a Pt temperature sensor (Sect. 4.3). The Pt-elements had to be passivated for protection and electrical insulation, so that a local deposition of a silicon-nitride passivation through a mask was performed. This silicon-nitride layer also can be varied in its thickness and with regard to its stress characteristics (compressive or tensile). This hotplate allowed for reaching operation temperatures up to 500 °C and it showed a thermal resistance of 7.6 °C/mW. 

Figure 12. Hydrogen concentration versus temperature for silicon nitride layers deposited by PECVD. (seem is standard cubic centimeters per minute.) (Reproduced with permission from reference 221. Copyright 1985 The Electrochemical Society, Inc.)...

A planar optical waveguide was integrated within a PDMS chip for fluorescent detection. The waveguide consists of a 150-nm-thick silicon nitride layer deposited on a 2.1-pm-thick Si02 buffer layer on a Si substrate. The rabbit IgG was... 

W.M., Influence of deposition temperature, gas pressure, gas phase composition, and RF frequency on composition and mechanical stress of plasma silicon nitride layer. J. Electrochem. Soc. 132 893 (1985). 

Passivation is needed to insulate the backplane from the OLED stacks everywhere except the ITO and bonding contact areas. Unlike poly-Si and a-Si H backplanes, on which both organic and inorganic passivation layers can easily work, the device passivation technique needs extra consideration for pentacene TFTs. We explored several different materials for passivation of pentacene TFTs, including poly(vinyl alcohol) (PVA), room temperature plasma-enhanced chemical vapor deposition silicon nitride (RT PECVD SiN), and vapor-deposited parylene. 

Another solution to reduce the loading effect was investigated by van Laarhoven et. al.61, (see figure 2.19). In their approach there was a 0.3 urn PECVD silicon nitride layer deposited atop the oxide prior to the contact opening. The normal procedure of adhesion layer (TiW), tungsten deposition and etch back was followed. Since the nitride etches with about the same rate as the tungsten (selectivity W SiN=0.8) both the loading is... 

Multicrystalline silicon wafers, with crystal sizes in the range 1-100 mm, ° are currently the main workhorse for the photovoltaics industry. Hydrogen passivation steps used in cell manufacture in recent years, particularly those involved in the deposition of silicon nitride layers on front surfaces, have reduced the impact of electrically active impurities and defects in MC-Si cells and reduced the performance deficit relative to monocrystalline cells. 

In the following, a silicon nitride layer was deposited as the gate dielectric on a thermally oxidised silicon wafer. The nitride layer was re-oxidised to enhance the electrical stability. The silicon dioxide below the nitride film adopted the function of a buffer layer to reduce mechanical stress between the silicon and silicon nitride due to different thermal coefficients of expansion. To deposit the dielectric film, ammonia gas and triethylsilane were put into the process tube in a ratio of 1 5, at 800 °C and at a process pressure of 0.3 mbar. The thickness of the deposited dielectric film was about 75 nm in total. 

The intrinsic stress in silicon nitride layers is important especially in micromechanical devices the characteristic features of membranes based on silicon nitride or thin silicon structures covered with silicon nitride are very sensitive to stress variations in these layers. Similar to PECVD-oxide, the intrinsic stress of silicon nitride is influenced by several deposition parameters such as gas flow, deposition temperature, and radiofrequency (RF) power. 

Amorphous silicon nitride films, which are resistant to water vapor, salts, and other chemicals and, therefore, are applied as a final encapsulating layer for ICs, are effectively produced using PECVD. A typical feed-gas mixture for PECVD is SiH4-NH3. The process is performed in plasma at pressures of 0.25-3 Torr conventional substrate temperatures are in the range 250-500°C. Deposition rates of silicon nitride films under such conditions are about 20-50 nm/min. The plasma deposited silicon nitride film can usually be characterized... 

In addition to realize smaller patterns with the same cross-sectional area, a silicon nitride layer was deposited on the surface after anisotropic etching of the deep trenches. The polymer was then deposited, and the silicon was etched by the isotropic process (only SFs). The results are shown in Fig. 12c, d. In this case, the patterns with a minimum lateral width of 5 pm are realized. 

Oxidation (of Siiicon), Fig. 6 (a-d) Schematic of a typical LOCOS formation process, (e) SEM image of a LOCOS structure. Note that the silicon nitride layer on the right-hand side was stripped and a polysilicon layer has been deposited on top of the structure to provide better contrast in the image (Image courtesy of J. Bravman, Stanford University)... 

CVD and physical vapour deposition processes, and the resulting crystal structures, have been much studied and used to deposit silicon nitride films and grow epitaxial layers as electrical insulators and as masks for the deposition of other materials in electronic integrated circuitry. 

The silicon resistor is defined in microcrystalline or single-crystal silicon and usually encapsulated in silicon nitride. The thickness of the deposited silicon nitride on either side of the cantilever is adjusted so that the neutral axis of the cantilever lies inside the silicon nitride layer rather than in the silicon layer. This asymmetry in material composition ensures that the resistor is placed close to one of the cantilever surfaces for optimal sensitivity. In addition, the silicon nitride serves as... 

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