Through-mask deposition process

The selective Cu deposition process was suggested by Ting and Paunovic (13) as an alternative means of fabricating multilevel Cu interconnections (Fig. 19.4). The first step in this through-mask deposition process (14) is the deposition of a Cu seed layer on a Si wafer, and then a resist mask is deposited and patterned to expose the underlying seed layers in vias and trenches. In the next step, Cu is deposited to fill the pattern. After the Cu deposition mask is removed, the surrounding seed layer is etched and dielectric is deposited. Electroless Cu deposition has been suggested for the blanket and selective deposition processes (15). 

Figure 19.4. Through-mask deposition process (a) Si substrate (b) Cu seed layer deposition (c) photoresist deposition and patterning (d) through-mask electroless deposition of Cu (e) stripping of photoresist and etching of Cu seed layer outside line (f) dielectric deposition.

In this section, we review the present manufacturing processes and discuss the challenges facing the extendability of these processes to the new generation of IC products. There are three primary fabrication processes (1) metal-reactive ion etching (RIE), (2) dielectric RIE, or damascene, and (3) through-mask deposition process. 

There is a basic difference between the damascene and through-mask plating processes in the way the trenches and vias are filled with electrochemically deposited Cu, through either an eiectrodeposition or an electroless technique. In multilevel metal structures, vias provide a path for connecting two conductive regions separated... 

Figure 19.6. Growth of deposit in vias and trenches during Cu electrodeposition in (a) damascene and (b) deposition through- mask process.

Preferred growth from the bottom may be achieved by the addition of suitable additives. In the plating through mask process only the bottom is active wliile the sidewalls are inactive, resulting in the grow of Cu deposit from the bottom, as depicted in Fig. 

Figure 17.11. Process steps for forming Cu interconnects using the single damascene process (dielectric patterning) (a) planarized substrate (b) dielectric deposition (c) dielectric RIE through photoresist mask (d) etched insulator (e) deposition of diffusion barrier (Ta) and Cu seed layer (/) electrodeposition of Cu into a via (vertical interconnection) ( ) CMP of Cu excess Qi) patterning and deposition of Cu line (wire).

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