Conductor lines

As PWB technology is refined to provide greater integration using finer conductor lines, there is renewed interest in hquid resists. The absence of a cover sheet and the abihty to apply thinner films both contribute to improved resolution and to an intrinsically lower consumables cost (16,17). 

With recent trends toward microminiaturization and utilization of very thin conductor lines, close spacings, and very thin insulation, greater demands are being placed on the insulating layer. Reductions in such parasitic capacitance can... 

The velocity of pulse propagation in these structures is inversely proportional to the square root of the dielectric constant of the medium [1]. Hence, reductions in the dielectric constant of the insulator materials translate directly into improvements in machine cycle time. The pitch or distance between conductor lines must, therefore, be minimized to improve cycle time. The minimum dis-... 

Equation 7 shows that the package size is directly proportional to the conductor line pitch (d) and the number of chip and package I/Os and inversely proportional to the number of layers (n). 

Propagation Delay of Lossless Lines. The minimum propagation delay (Tpd expressed in picoseconds per centimeter) for a unit length of lossless line is the inverse of the phase velocity (op) of the electromagnetic waves propagating through the dielectric medium surrounding the conductor line ... 

In summary, the main advantages of thick-film technology are the high-conductivity conductors and the relatively inexpensive process equipment, whereas the drawbacks are the limited number of layers, the multiple printing and firing steps, the low conductor line resolution, and the limited dielectric thickness. 

In the lift-off process, a blanket metal coating is deposited, usually by evaporation, over the photoresist, which is then dissolved to lift off the unwanted metal and leave the desired pattern. The lift-off process may be assisted by depositing and patterning a dielectric layer, a release layer, or both beneath the photoresist (131, 132). In both additive approaches, via posts are patterned in a step separate from that used to pattern the conductor lines. The polyimide is then coated over the lines and via posts, and shallow etching or mechanical polishing is done to expose the top of the via posts. The process sequence is then repeated to pattern additional layers. 

Comparison of Approaches. The additive processes can achieve conductor features with a large aspect ratio, although selective plating can create a negative side wall angle in the conductor that reduces the spacing between conductor lines and that is is difficult to coat with polymer dielectrics. Elec-... 

A final alternative for metal patterning is the use of lasers to selectively and accurately etch small metal areas. Lasers are routinely used to trim thin-film resistors (126) they may also be used to repair defects or etch conductor lines by direct ablation in an inert atmosphere (127,129) or by laser-initiated etching in a reactive gas or liquid (128). 

Conductor lines must be narrow to maximize the space/linewidth ratio and thus minimize the crosstalk between adjacent lines. The lines must also have a large cross-section, and thus a high aspect ratio (thickness/width), to minimize resistive losses which attenuate signals and increase signal risetimes. High conductivity conductor materials are also desirable for low resistive losses. 

Polyamic acid (PAA) solutions are deposited by either spinning or spraying. They are cured by heating at a controlled rate from 50 C to 350-420 C to evaporate solvents and reaction products (primarily H2O) and convert the PAA to PI. Multiple coats are deposited to achieve the thick (20-40 pm) planarized dielectric layers required for high Impedance TFML interconnects. Figure 3 shows a cross-section of 5 pm thick conductor lines planarized with 25 pm (three coatings) of spray-coated PI. 

Figure 3 Cross-section of 5 urn thick conductor lines on ceramic, coated with 25 urn of polyimide.

K. K. Chakravorty, C. P. Chien, J. M. Cech, M. H. Thnielian, and P. L. Young, High-Density Interconnection Using Photosensitive Polyimide and Electroplated Copper Conductor Lines, IEEE Comp., Hybrids., Manuf. Technol., 13, No. 1, pp. 200-206 (1990). 

Metal-RIE process was/is used in the fabrication of Al inter-coimects on chips." This process is depicted in four steps in Fig. 2. The first step in the metal-RIE process is sputter deposition of a blanket thin film of Al (or Al alloys, such as Al-Cu, Al-Si) over a planerized dielectric (e.g., silicon dioxide). In the next step, the unwanted metal is etched away by reactive ion etching (RIE) through a photoresist mask. The features produced this way are separated, electrically isolated, metal Al conductor lines. In the RIE process chemicaly active ions such as F or Cl bombard the Al surface and form volatile aluminum fluorides or chlorides, which are then pumped away in the vacuum system. After etcliing, a dielectric is deposited in such a fashion that it fills the gaps between the lines as well as above them. In the last step, the dielectric is planarized using the chemical mechanical polishing (CMP) technique. ... 

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