Silicon wafer, thermal processing

H. Takeno, T. Otogawa, Y. Kitagawara. Practical computer simulation technique to predict oxygen precipitation behavior in Czochralski silicon wafers for various thermal processes. J Electrochem Soc 144 4340, 1997. 

Conventional electronic devices are made on silicon wafers. The fabrication of a silicon MISFET starts with the diffusion (or implantation) of the source and drain, followed by the growing of the insulating layer, usually thermally grown silicon oxide, and ends with the deposition of the metal electrodes. In TFTs, the semiconductor is not a bulk material, but a thin film, so that the device presents an inverted architecture. It is built on an appropriate substrate and the deposition of the semiconductor constitutes the last step of the process. TFT structures can be divided into two families (Fig. 14-12). In coplanar devices, all layers are on the same side of the semiconductor. Conversely, in staggered structures gate and source-drain stand on opposing sides of the semiconductor layer. 

Organic coatings are also possible. The classic example is the paralene process where a cyclic dimer of p-xylene is thermally decomposed at about 850°C to form /i-xylene free radicals that polymerize into a conformal film when deposited on a solid surface. Other examples of polymerization from a deposited vapor have been developed, and advocates believe that this technology will replace spin coating of silicon wafers. 

As an example of the latter technique, Volkman et al. demonstrated the feasibility of using spin-cast zinc oxide nanoparticles encapsulated in 1-dodecanethiol to fabricate a functional transistor.44 The zinc oxide was deposited on a thermally grown silicon dioxide layer on a conventional silicon wafer, with thermally evaporated gold source and drain electrodes. As reported, the process requires very small particles (3nm or less) and a 400 °C forming gas anneal. A similar approach was also reported by Petrat, demonstrating n-channel thin-film transistor operation using a nanoparticle solution of zinc oxide dispersed onto a thermally grown silicon dioxide layer on a conventional... 

Silicon is a widely investigated substrate because it has a relatively high thermal conductivity and a perfect CTE match to silicon die. In addition, silicon wafers have a high-quality surface finish and are widely available in standard sizes that are adaptable to IC process equipment. However, silicon has a low modulus and a poor CTE match to polyimides, and thus, very thick substrates will be required to prevent excessive warpage. A final advantage of silicon substrates is that active devices such as driver circuits may be fabricated in the substrate. 

Xie et al. [20] reported the fabrication chip for pumps and an electrospray nozzle. The process used to fabricate the electrochemical pump chips with electrospray nozzle is shown in Fig. 2.11. A 1.5 xm layer of Si02 was grown on the surface of a 4 inch silicon wafer by thermal oxidation. The front side oxide layer was patterned and removed with buffered FIF. XeF2 gaseous etching was used to roughen the silicon surface in order to promote the adhesion between subsequent layers and the substrate. The first 4.5 p,m parylene layer was deposited. 

In the semiconductor industries, a number of materials are deposited on silicon wafers using CVD technologies such as plasma-CVD and thermal-CVD as described in the previous section. As the CVD process is repeated, a thick film is inevitably deposited on the various parts of the chamber and the internal walls of the exhaust tubes. This thick film generates contamination particles that affect the electrical resistance of the devices. Accordingly, cleaning of the apparatus is periodically necessary to eliminate the deposits and to improve the reliability of the device. 

The liquid solution CCVD process does not deposit droplets (these evaporate in the flame environment) or powders as in traditional thermal spray processes. The CCVD technology is drastically different from spray pyrolysis In spray pyrolysis, a liquid mixture is sprayed onto a heated substrate, while CCVD atomizes a precursor solution into sub-micron droplets followed by vaporization of said droplets. The resulting coating capabilities and properties described hereafter qualifies CCVD as a true vapor deposition process. For example, depositions are not line-of-sight limited and achieve epitaxy, 10 nm dielectric coatings onto silicon wafers in a Class 100 clean room resulted... 

The deposition processes discussed so far typically operate such that all the material required for the growing film comes from the overlying gas or liquid phase. Other deposition reactions involve reaction (and therefore consumption) of the underlying substrate itself. Examples of such deposition processes include thermal oxidation, nitridation, or silicidation of silicon, which can be accomplished by exposing a silicon wafer at high temperature to oxygen, ammonia, or titanium tetrachloride, respectively, to form silicon dioxide, silicon nitride, or titanium disilicide. Solid-phase diffusion and reaction processes are involved in each case. 

In the following, a silicon nitride layer was deposited as the gate dielectric on a thermally oxidised silicon wafer. The nitride layer was re-oxidised to enhance the electrical stability. The silicon dioxide below the nitride film adopted the function of a buffer layer to reduce mechanical stress between the silicon and silicon nitride due to different thermal coefficients of expansion. To deposit the dielectric film, ammonia gas and triethylsilane were put into the process tube in a ratio of 1 5, at 800 °C and at a process pressure of 0.3 mbar. The thickness of the deposited dielectric film was about 75 nm in total. 

In our study, a three-layered Al/Cu/Ti film was employed as the seeding layer for electroless Cu deposition process. These metal films were deposited using the electron-beam evaporation technique and the substrates employed were thermally oxidized <100> silicon wafers. Ti is employed as the first layer, to serve as a barrier/adhesion promotion layer since Ti adheres well to most dielectric substrates and can prevent Cu diffusion into Si02. The second layer, Cu is the best homogenous catalyst for electroless Cu deposition. The last layer, A1 is a sacrificial layer to prevent Cu oxidation before immersing into the electroless deposition solution. 

For thin-film metallization, a thin metallic film is first deposited onto the surface of the substrate. The deposition can be accomplished by thermal evaporation, electronic-beam- or plasma-assisted sputtering, or ion-beam coating techniques, all standard microelectronic processes. A silicon wafer is the most commonly used substrate for thin-film sensor fabrication. Other substrate materials such as glass, quartz, and alumina can also be used. The adhesion of the thin metallic film to the substrate can be enhanced by using a selected metallic film. For example, the formation of gold film on silicon can be enhanced by first depositing a thin layer of chromium onto the substrate. This procedure is also a common practice in microelectronic processing. However, as noted above, this thin chromium layer may unintentionally participate in the electrode reaction. 

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