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Three-layer RIE PCM

Figure 19. Si02 lines on the RIE d planarizing layer crosses over topo graphic features on the wafer. The Si02 three-layer RIE PCM was used to delineate these 1.0-u lines. (Reproduced with permission from Ref. 34.)... Figure 19. Si02 lines on the RIE d planarizing layer crosses over topo graphic features on the wafer. The Si02 three-layer RIE PCM was used to delineate these 1.0-u lines. (Reproduced with permission from Ref. 34.)...
MLR systems can be classified by the number of layers and the function of the PCM, e.g., two-layer RIE PCM. Some authors prefer to use "bi-level," "tri-level," "double-layer," "triple-layer," or any other permutation of these words to denote the number of layers. The word "layer" and simple numerical adjectives are used here, because "level" may cause confusion because of its association with masking levels and because simple numerical adjectives pronounce better when the number of layers exceeds three. [Pg.288]

Figure 13a shows the resist in a three-layer Al-RIE-PCM system by Havas et al. The dry etching conditions were similar to those of plasma etching. Therefore, an undercut was produced under the Al PCM to facilitate lift-off. Figure 13b shows the resist image in a three-layer siloxane RIE PCM system. The dry etching process was sufficiently anisotropic to eliminate the undercut. [Pg.303]

The three-layer deep-UV PCM system of Lin and Chang 34) used A1 as a deep-UV PCM instead of Si02 as the RIE PCM. This eliminates the need for an RIE system but still requires a large number of processing steps. Figure 20 shows a 0.3 - pm thick A1 deep-UV PCM on 1.6 pm of PMMA. [Pg.311]

TABLE VI. Processing Steps of the Three-Layer Si02 RIE PCM System... [Pg.312]


See other pages where Three-layer RIE PCM is mentioned: [Pg.311]    [Pg.314]    [Pg.317]    [Pg.183]    [Pg.196]    [Pg.311]    [Pg.314]    [Pg.317]    [Pg.183]    [Pg.196]    [Pg.302]    [Pg.303]    [Pg.305]    [Pg.314]    [Pg.328]    [Pg.330]    [Pg.342]   


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