Silicon oxidation process step, integrated

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

These process steps, as practiced for the trench isolation process, are either new or modifications or extensions of previously practiced processes used for other aspects of device fabrications. Consequently, several of these steps did require general process development on an individual basis, prior to their integration into the overall process. Some of the efforts have resulted in new basic knowledge in the area of reactive ion etching (RIE) and chemical vapor deposition, surface planarization with resist materials, and thermal oxidation or nonplanar silicon surfaces. The author has previously presented various aspects of these process activities (4-8), as applied to the bipolar device technology. 

The most commonly implemented and extensively investigated CMP steps are the preparation of planar premetal dielectrics (PMD) and interlayer dielectrics (ILD) films on wafer. Together they are labeled as oxide CMP, as they both use the same materials that are based on silicon dioxide. Both processes share the integration concerns in deposition, planarity, and defectivity. 

The chemical component of CMP slurry creates porous unstable oxides or soluble surface complexes. The slurries are designed to have additives that initiate the above reactions. The mechanical component of the process removes the above-formed films by abrasion. In most planarization systems the mechanical component is the rate-limiting step. As soon as the formed porous film is removed, a new one is formed and planarization proceeds. Therefore, the removal rate is directly proportional to the applied pressure. To achieve practical copper removal rates, pressures greater than 3 psi are often required. These pressures should not create delamination, material deformation, or cracking on dense or relatively dense dielectrics used in silicon microfabrication on conventional dielectrics. However, the introduction of porous ultra-low-fc (low dielectric constant) materials will require a low downpressure (< 1 psi) polishing to maintain the structural integrity of the device [7-9]. It is expected that dielectrics with k value less than 2.4 will require a planarization process of 1 psi downpressure or less when they are introduced to production. It is expected that this process requirement will become even more important for the 45-nm technology node [10]. 

One of the first and die most widely used CMP process, aside from the final step in the preparation of silicon wafers, is oxide CMP for back-end planarization after the initial oxide ILD deposition and between metal levels. As a result, oxide CMP is the most mature process, with the most fundamental studies having been performed in this area. Indeed, much of our understanding of the CMP of metals and other materials is derived from our understanding of oxide CMP. This chapter first presents the current understanding of the oxide CMP fundamentals. The discussion includes the mechanisms of both mato-ial removal and surface planarization. The second part of the chapter is devoted to the practice of oxide CMP, including reported results on planarization and polish rate performance of oxide CMP processes in industry. In addition, process integration, cost of ownership, manufacturability, and yield issues will be discussed. 

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