Planar processes

In general, in a planar process, — junctions are formed just below the surface of a siUcon wafer by the implantation of donor ions into a type region or acceptor ions into an n-ty e region. Thus, the general concern is with -p or -n junctions. As the initial wafer concentration of acceptors or donors in sihcon increases from 10 to 10 cm increases from about 0.81 to 1.04 V for a p n junction and is about 10 mV higher for an -p... 

Among numerous planarization technologies, CMP provides a global planarization of topography with a low post-planarization slope [97,98]. It can also dramatically reduce topographical variations to a degree not possible with any other planarizing process [97,99,100]. 

Figure 1. Schematic drawing of two planarization processes using (A) a low molecular weight polymeric resin and (B) a low viscosity, liquid monomer.

The ideal deposition process would leave a perfectly flat surface. That does not happen, so a planarization process is required to maintain depth of field requirements. For a dielectric planarization process, the ideal planarization process would remove only material in the up areas and remove no material in the down areas. Metal CMP involves the removal of metal overburden, leaving filled plugs or vias (single damascene) or filled vias and inlaid metal lines (dual damascene) with no removal of metal in the inlaid region and no removal of dielectric. 

A. Hu, X. Zhang, E. Sachs, P. Renteln, Application of Run by Run Controller to the Chemical-Mechanical Planarization Process, IEEE Proceeding of the 15th International... 

D. Bramano and L. Racz Numerical Flow-Visualization of Slurry in a Chemical Mechanical Planarization Process, Proc. of CMP-MIC, pp. 185-192, Santa Clara, CA, Feb. 1998. 

C. Yu, P. C. Fazan, V. K. Mathews, and T. T. Doan, Dishing Effects in a Chemical Mechanical Polishing Planarization Process for Advanced Trench Isolation, Appl. Phys. Lett., vol. 61, no. 11, pp. 1344-1346, Sept. 1992. 

Tutorial, Planarization Processes for ULSl Fabrication to the Year 2002 (SEMICON WEST, July 16, 1997) p. 51. 

Other authors have produced multi-ion chemfets. Matsuo and Esashi have demonstrated that multi-ion ehemfet structures can be planar processed in a two-ion needle shaped form (48). Their ingenious needle shaped design permits them to incorporate two or possibly three sensitive elements at the tip. However, the demands of electrical and chemical isolation become increasingly difficult as the number of ion sensitive elements increases in these devices. Pace has demonstrated that a pH sensitive element, combined with a multilayer composite structure, can be used to detect a wide range of chemical species (56). This concept is quite versatile and has been proposed as the means to extend the capability of the pH sensitive... 

A detector structure which may be fabricated by planar processing and which permits fabrication of thin infrared detectors is shown in US-A-4197633. 

The antenna in an RFID is typically implemented as a spiral inductor or as a dipole antenna, depending on the frequency of operation of the tag. This frequency of operation depends on the application, government-imposed standards, physical constraints, etc. The most common frequencies for operating RFID tags are <125 kHz (called the LF band), 13.56 MHz (called the HF band), 900 MHz (called the UHF band), and 2.4 GHz (called the microwave band). For various reasons, 125 kHz tags are not compatible with planar processing and thus will not be considered here. 

Why is tribology important for the chemical-mechanical planarization process ... 

In a computer hard drive, the data are stored on one or more rigid disks coated with magnetic materials. The magnetic film is coated on a planar NiP substrate. NiP film is typically electroplated on an aluminum disk. Before the coating process, the NiP must be planarized. The planarization process is similar to oxide ILD CMP except that the material is a metal. The slurry chemistry is similar to copper or tungsten CMP except that the end point is to form a perfectly planar substrate. Hydrogen peroxide can be used as an oxidizer in NiP CMP as stated in the patent by Jia and coworkers [14,15]. As shown in Fig. 7.5, the removal rate for NiP film follows the same trend as for copper. At higher concentration, the removal rate decreases because of the formation of a native protective NiO film [12]. 

The chemical component of CMP slurry creates porous unstable oxides or soluble surface complexes. The slurries are designed to have additives that initiate the above reactions. The mechanical component of the process removes the above-formed films by abrasion. In most planarization systems the mechanical component is the rate-limiting step. As soon as the formed porous film is removed, a new one is formed and planarization proceeds. Therefore, the removal rate is directly proportional to the applied pressure. To achieve practical copper removal rates, pressures greater than 3 psi are often required. These pressures should not create delamination, material deformation, or cracking on dense or relatively dense dielectrics used in silicon microfabrication on conventional dielectrics. However, the introduction of porous ultra-low-fc (low dielectric constant) materials will require a low downpressure (< 1 psi) polishing to maintain the structural integrity of the device [7-9]. It is expected that dielectrics with k value less than 2.4 will require a planarization process of 1 psi downpressure or less when they are introduced to production. It is expected that this process requirement will become even more important for the 45-nm technology node [10]. 

The copper-clearing step is a conventional planarization process. This step introduces most of the topography on the wafer. The two main reasons are the dependency of the copper removal rate on the wafer pattern density and the fact... 

FIGURE 11.20 Final topography comparison between wafers after a conventional and an ECMP planarization process, where slurry C is used in the barrier removal (from Ref 25). 

The introduction of silicon-on-insulator (SOI) technologies in manufacturing as a way of decreasing parasitic leakages and capacitances in MOS devices will alleviate the planarization process because of the reduced trench depth and consecutively reduced initial step height. 

Boyd JM, Ellul JP. A one-step shallow trench global planarization process using chemical mechanical polishing. ECS Proc 1996 95-5 290. 

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