Shallow trench isolation process

Lin CF, Tseng W, Fengand M, Wang Y. A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarization. Thin Solid Films 1999 22 248-252. 

Fig. 7 Shallow trench isolation processing. (View this art in color at www.dekker.com.)...

MOSFETT s, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. For shallow trench isolation, anisotropic silicon etch, thermal oxidation, oxide fill and chemical mechanical leveling are the processes employed. For shallow source/drains formation, ion implantation techniques are still be used. For raised source/drains (as shown in the above diagram) cobalt silicide is being used instead of Ti/TLN silicides. Cobalt metal is deposited and reacted by a rapid thermal treatment to form the silicide. Capacitors were made in 1997 from various oxides and nitrides. The use of tantalmn pentoxide in 1999 has proven superior. Platinum is used as the plate material. 

The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. 

B. Withers, E. Zhoa, R. Jairath, A Wide Margin CMP and Clean Process for Shallow Trench Isolation Applications, 1998 Proceedings of the Third International Chemical-Mechanical Planarization for VLSI Multilevel Interconnection Conference (CMP-MIC), Santa Clara, CA, pp. 319-327, Feb. 19-20,1998. 

A key benefit of accurate CMP models that needs emphasis is the capability to optimize layout design before polishing. Post-CMP ILD thickness variation is a serious concern from both functionality and reliability concerns. An effective method of minimizing this effect is the use of dummy fill patterns that lead to a more equitable pattern density distribution across the chip. Evaluation of such schemes before actual product implementation has become a major use of CMP modeling [53]. Dummy fill is also being investigated for front-end processes where shallow trench isolation CMP suffers from substantial pattern dependencies. 

Another important microstructure in IC manufacturing process is shallow trench isolation (STI) that allows the effective separation of active devices and increase of packing densities. Figure 1.23 shows a schematic of an STI structure before and after polishing [51]. It is important for the dishing of the oxide in the trench and the nitride loss to be as low as possible. 

Chatterjee A, Ali I, Joyner K, Mercer D, Kuehne J, Mason M, Esuivel A, Rogers D, O Brien S, Mei P, Murtaza S, Kwok SP, Taylor K, Nag S, Hames G, Hanratty M, Marchman H, Ashburn S, Chen I-C. Integration of unit processes in a shallow trench isolation module for a 0.25 pm complementary metal-oxide semiconductor technology. J Vac Sci Technol 1997 B15(6) 1936-1942. 

Chatterjee A, Kwok SP, Ali I, Joyner K, Shinn G, Chen I-C. Chemical mechanical planarization (CMP) process windows in shallow trench isolation for advanced CMOS. Electrochem Soc Proc 1996 96-22 219-227. 

FIGURE 13.1 Illustrations of the various processing steps for local oxidation of silicon and shallow trench isolation (from Ref. 7). 

Bonner BA, Iyer A, Kumar D, Osterheld TH, Nickles AS, Flynn D. Development of a direct polish process for shallow trench isolation modules. CMP-MIC 2001. 

Burkhard C. Characterization of advanced shallow trench isolation (STI) CMP Processes and consumables. Ph.D. Thesis 2006. 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

Among other process tq)plications are the use of CMP to improve shallow trench isolation. Bird s beak planarization, and stacked or trench capacitor. 

J. Schlueter, I. Kim, F. J. Krupa, The Effect of Consumables in the Development of Advanced Shallow Trench Isolation (STI) CMP Processes, Proceedings of Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC), 1999, pp.336-339... 

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