Polysilicon process

Polysilicon. Polysihcon is used as the gate electrode material in MOS devices, as a conducting material for multilevel metallization, and as contact material for devices having shallow junctions. It is prepared by pyrolyzing silane, SiH, at 575—650°C in a low pressure reactor. The temperature of the process affects the properties of the final film. Higher process temperatures increase the deposition rate, but degrade the uniformity of the layer. Lower temperatures may improve the uniformity, but reduce the throughput to an impractical level. 

NAA has been used to determine trace impurities in polysilicon, single-crystal boules, silicon wafers, and processed silicon, as well as plastics used for packaging. ... 

An example of an analysis done on polysilicon and single-crystal Czochralski silicon (CZ) is shown in Table 1. As can be seen, polysilicon, which was used to grow the crystal, is dirtier than the CZ silicon. This is expected, since segregation coefficients limit the incorporation of each element into the crystal boule during the crystal growth process. All values shown in the table are from bulk analysis. Table 2 shows NAA data obtained in an experiment where surface analysis was accom-... 

Thermal nrocessing- Difiusion furnaces are used not only for the anneal of implanted dopants but for growing high quality thermcd oxides, depositing polysilicon nitride films (SiN,) and for rapid thermcd processing of deposited films. 

Metal and polysilicon films are formed by a chemical-vapor deposition process using organometallic gases that react at the surface of the IC structure. Various metal silicide films may also be deposited in this manner by reaction with the surface of the silicon wafer to form metal silicides. Glass and pol3uner films are deposited or spin cast or both, as are photoresist films (those of a photosensitive material). This process is accomplished by applying a liquid polymer onto a rapidly rotating wafer. The exact method used varies from manufacturer to manufacturer and usually remains proprietary. 

The material properties of PS offer new ways of making electronic devices. For the manufacture of cold cathodes, for example, oxidized microporous polysilicon has been found to be a promising material. The application of basic semiconductor processing steps such as doping, oxidation and CVD to a macroporous material enable us to fabricate silicon-based capacitors of high specific capacitance. Both devices will be discussed below. 

A schematic view of the cold cathode fabrication process is shown in Fig. 10.18. The cold cathode is fabricated by low pressure chemical vapor deposition (LPCVD) of 1.5 pm of non-doped polysilicon on a silicon wafer or a metallized glass substrate. The topmost micrometer of polysilicon is then anodized (10 mA cnT2, 30 s) in ethanoic HF under illumination. This results in a porous layer with inclusions of larger silicon crystallites, due to faster pore formation along grain boundaries. After anodization the porous layer is oxidized (700 °C, 60 min) and a semi-transparent (10 nm) gold film is deposited as a top electrode. 

Fig. 10.18 Schematic view of the fabrication process of a porous polysilicon-based cold cathode. Note that metallized glass may also serve as a substrate. Redrawn from [Ko21].

A novel microhotplate design was proposed to overcome the CMOS operating temperature limit and to avoid polysilicon-induced drift problems. A cross-sectional schematic of the device is shovm in Fig. 4.11. Instead of using a polysilicon resistor as temperature sensor, a platinum temperature sensor is patterned on the microhotplate. The Pt-metallization process step was used to simultaneously fabricate the electrodes and the temperature sensor. The CMOS-Al/Pt contacts are located off the membrane... 

Emphasis in CMP technology in 1998-1999 has evolved from a nearly exclusive focus on traditional polish systems to the use in manufacturing of advanced second- and third-generation polishers. This advance in technology has translated into standard CMP processes for oxide, polysilicon, and tungsten CMP, and expanded interest in aluminum CMP, copper CMP,... 

In reflectometry, the light passes through the films to be measured. Beneath the transparent films, there must be an opaque substrate through which light does not pass. The substrate characteristics must be modeled correctly to calculate the thicknesses of the films above. In silicon processing, theoretically, any of the commonly used metal materials, such as the titanium nitride (TiN), aluminum (Al), and tungsten (W), can be used as substrates. However, in reality, whereas a PMD oxide can be measured on the polysilicon material used in poly interconnections, an ILD oxide can not be measured directly on TiN, because the TiN layer used is too thin to be opaque. TiN is semitransparent if its thickness is less than 1000 A. A thin... 

To measure the final oxide thickness in the PMD process, the measurement sites can be set up over field oxide or over the polysilicon interconnections (see Fig. 6). However, since there are fewer variables in measuring over the field oxide, and the field oxide process is relatively well established, the PMD thickness is more accurately measured over the field oxide. If the measurement is over the polysilicon, the resultant PMD thickness measured can be affected by the deposited polysilicon thickness, the polysilicon doping, and the field oxide thickness variation, while if the measurement is over the field, the PMD thickness is affected only by the field oxide thiekness. 

The same is true for the STI process, because after the CMP and the nitride strip, polysilicon is deposited. Polysilicon is also an opaque material, and if the nonplanarity is not present or reduced, the stepper cannot locate the alignment mark to align the polysilicon pattern to the STI pattern. 

The substrate for this CVD process is a thin silicon rod, called a slim rod, which serves as a nucleation site for the depositing silicon. After deposition, the EGS, or polysilicon, is processed in the Czochralski (CZ) growth process. 

Fig. 13. (a) The CMOS inverter circuit. The FET circuit symbols emphasize that MOSFETs are actually four-terminal devices in which the -substrate is connected to b DD for the PFET and the -substrate is connected to the ground for the NFET. Note the conventions on drain location for the PFET and NFET. (b) Corresponding cross-sectional view roughly to scale for a 2-Jim CMOS process, where Brepresents silicon, D Si02, fZl polysilicon, and Q... 

Polysilicon subtrates are usually encountered during MOS device fabrication for defining gate structures. For submicrometer CMOS processing, adhesion problems encountered with this substrate are even more severe. 

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