Polysilicon, deposition

Others have reached similar conclusions, with Duchemin etal. [23] showing that at the low pressures used for polysilicon deposition the hydrogen is... 

In Section 17.3.2(i) we have indicated a range of uses for polysilicon. For all of these applications there is a need to control layer structure. In addition, careful control of doping levels is also necessary. This can be done with post-deposition doping but this requires a high temperature (typically >900°C) in order to move the dopant atoms from the surface and to drive them into the layer. This high temperature diffusion step can cause thermal damage. One solution is to use in situ doping at the normal temperature of polysilicon deposition i.e., ca. 600°C. 

Deposition temperatures of typically 550-650°C and reactor pressures in the range 15-130 Pa (0.1-1 Torr) are comparable to those used for undoped polysilicon deposition. Flow rate ratios (-y) of PHySil from 10-5 to 10-1 have been reported, but the most commonly used range is 10-3-10-2. 

Fig. 17.10. Predicted and experimental growth rates for doped polysilicon deposition for various reaction conditions (a) deposition temperature 625°C, y = 4 x 10 3 (b) deposition temperature 650°C, y = 2 x 10 3 [20],...

One company is modifying the final polysilicon deposition step in the Siemens process. The new method uses a graphite pipe heated to 1500°C, beyond... 

Fig. 5.2.7 Wafer cross section after mechanical polysilicon deposition and etching...

Figure 1.7 PolyMUMPS three-layer polysilicon surface micromacliming process offered by MEMSCAP. Polysilicon and oxide layers are deposited and patterned in a cyclic process, with anneal steps of the doped saciilicial oxide between polysilicon depositions. PolyO is an electrical layer that is not released. Polyl and Poly2 are structural layers that can be released. The deposition and patterning steps shown here result in a polysiUcon wheel defined in Polyl that is constrained by a hub defined in Poly2. Dimples defined in POLYl keep the wheel from becoming stuck to the PolyO layer. (Reprinted with permission from MEMSCAP Eic.) See color plate section.

Figure 1.11 SUMMIT V cross section. The SUMMiT V process features five layers of polysilicon, four of which can be released. The upper layers of sacrificial oxide are polished, removing the topography that develops during the conformal polysilicon depositions. (Courtesy of Sandia National Laboratories, SUMMiT(TM) Technologies, www.mems.sandia.gov.) See color plate section.

Polysilicon. Polysihcon is used as the gate electrode material in MOS devices, as a conducting material for multilevel metallization, and as contact material for devices having shallow junctions. It is prepared by pyrolyzing silane, SiH, at 575—650°C in a low pressure reactor. The temperature of the process affects the properties of the final film. Higher process temperatures increase the deposition rate, but degrade the uniformity of the layer. Lower temperatures may improve the uniformity, but reduce the throughput to an impractical level. 

Polysilicon is a contraction of polycrystalline silicon, (in contrast with the single-crystal epitaxial silicon). Like epitaxial silicon, polysilicon is also used extensively in the fabrication of IC s and is deposited by CVD.f l it is doped in the same manner as epitaxial silicon. Some applications of poly silicon films are ... 

The short penetration depth of UV/blue photons is the reason that frontside CCD detectors have very poor QE at the blue end of the spectrum. The frontside of a CCD is the side upon which the polysilicon wires that control charge collection and transfer are deposited. These wires are 0.25 to 0.5 /xm thick and will absorb all UV/blue photons before these photons reach the photosensitive volume of the CCD. For good UV/blue sensitivity, a silicon detector must allow the direct penetration of photons into the photosensitive volume. This is achieved by turning the CCD over and thinning the backside until the photosensitive region (the epitaxial layer) is exposed to incoming radiation. 

Figure 15. Photovoltaic detector potential well. The example in this figure is the p-n junction of a n-channel CCD. The x-y-z axes match the orientation shown in Fig. 5. The charge generated in the 3-D volume of a pixel is swept toward a 2-D layer, which is the buried channel that is 0.25-0.5 pm from the front surface of the detector. The z-direction potential is created by the p-n junction combined with the voltages on the polysilicon wires deposited on the frontside of the CCD (not shown in this figure).

Chemical Vapor Deposition- Deposition of silicon oxide films is accomplished by CVD equipment. Either plasma CVD or ozone oxidation is used. Blanket tungsten films are also deposited by CVD equipment to create contact and via plugs. Polysilicon and silicon nitride films are deposited in hot-wall furnaces. TiN diffusion barrier films are deposited by either sputtering or CVD, the latter giving superior step coverage. 

Thermal nrocessing- Difiusion furnaces are used not only for the anneal of implanted dopants but for growing high quality thermcd oxides, depositing polysilicon nitride films (SiN,) and for rapid thermcd processing of deposited films. 

Metal and polysilicon films are formed by a chemical-vapor deposition process using organometallic gases that react at the surface of the IC structure. Various metal silicide films may also be deposited in this manner by reaction with the surface of the silicon wafer to form metal silicides. Glass and pol3uner films are deposited or spin cast or both, as are photoresist films (those of a photosensitive material). This process is accomplished by applying a liquid polymer onto a rapidly rotating wafer. The exact method used varies from manufacturer to manufacturer and usually remains proprietary. 

A schematic view of the cold cathode fabrication process is shown in Fig. 10.18. The cold cathode is fabricated by low pressure chemical vapor deposition (LPCVD) of 1.5 pm of non-doped polysilicon on a silicon wafer or a metallized glass substrate. The topmost micrometer of polysilicon is then anodized (10 mA cnT2, 30 s) in ethanoic HF under illumination. This results in a porous layer with inclusions of larger silicon crystallites, due to faster pore formation along grain boundaries. After anodization the porous layer is oxidized (700 °C, 60 min) and a semi-transparent (10 nm) gold film is deposited as a top electrode. 

The temperature sensor in the membrane center is made of polysilicon with a nominal resistance of 10 kQ. An additional reference resistor is needed for the control circuitry (Sect. 5.1). For the resistance measurement of the sensitive layer, platinum electrodes are deposited on top of the CMOS aluminum metallization in order to establish good electrical contact to the sensitive metal oxide. 

The main goal of another microhotplate design was the replacement of all CMOS-metal elements within the heated area by materials featuring a better temperature stability. This was accomplished by introducing a novel polysilicon heater layout and a Pt temperature sensor (Sect. 4.3). The Pt-elements had to be passivated for protection and electrical insulation, so that a local deposition of a silicon-nitride passivation through a mask was performed. This silicon-nitride layer also can be varied in its thickness and with regard to its stress characteristics (compressive or tensile). This hotplate allowed for reaching operation temperatures up to 500 °C and it showed a thermal resistance of 7.6 °C/mW. 

To measure the final oxide thickness in the PMD process, the measurement sites can be set up over field oxide or over the polysilicon interconnections (see Fig. 6). However, since there are fewer variables in measuring over the field oxide, and the field oxide process is relatively well established, the PMD thickness is more accurately measured over the field oxide. If the measurement is over the polysilicon, the resultant PMD thickness measured can be affected by the deposited polysilicon thickness, the polysilicon doping, and the field oxide thickness variation, while if the measurement is over the field, the PMD thickness is affected only by the field oxide thiekness. 

The same is true for the STI process, because after the CMP and the nitride strip, polysilicon is deposited. Polysilicon is also an opaque material, and if the nonplanarity is not present or reduced, the stepper cannot locate the alignment mark to align the polysilicon pattern to the STI pattern. 

The substrate for this CVD process is a thin silicon rod, called a slim rod, which serves as a nucleation site for the depositing silicon. After deposition, the EGS, or polysilicon, is processed in the Czochralski (CZ) growth process. 

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