Dual damascene

Application(s) Si stock polish tungsten damascene CMP Si final polish CMP post-CMP buff Si stock ILD CMP metal dual damascene ILD CMP shallow trench Isolation metal dual damascene... 

Figure 19.3. Process steps for the dual damascene process (a) deposition of dielectric b) dielectric RIE to define via and line (c) deposition of diffusion barrier and Cu seed iayer (d) eiectrodeposition of Cu into via and trenches foiiowed by Cu CMP.

The ideal deposition process would leave a perfectly flat surface. That does not happen, so a planarization process is required to maintain depth of field requirements. For a dielectric planarization process, the ideal planarization process would remove only material in the up areas and remove no material in the down areas. Metal CMP involves the removal of metal overburden, leaving filled plugs or vias (single damascene) or filled vias and inlaid metal lines (dual damascene) with no removal of metal in the inlaid region and no removal of dielectric. 

FIGURE 1.15 Damascene and dual damascene techniques employed (from Ref. 45). 

Tungsten CMP, to a lesser extent, has also been utilized to construct tungsten lines as a part of the interconnect via damascene or dual-damascene... 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

Aruanchalam V, Smith G, Kailasam S, Knorr A, Hettiaratchi K, Rozbicki R, Pfeifer K, Ho P, Pyun J. Comparison of barrier-first and argon pre-clean first processes for copper metallization in ultra low-k (ULK) dual damascene integration. Proceedings of the Advanced Metallization Conference 2005 p 413-419. 

Alers G, Rozbicki R, Harm G, Kailasam S, Ray G, Danek M. Barrier-first integration for improved reliability in copper dual damascene interconnects. Proceedings of the IEEE International Reliability Physics Symposium 2003 ... 

Peterson ML, Small RJ, Shaw GA, Shen ZJ, Truong T. Investigating CMP and post-CMP cleaning issues for dual-damascene copper technology. Micro magazine 1999. 

Complete fill capabilities of sub-micron scale structures (dual damascene) with >1 10 aspect ratios, often with marginal seed layer. 

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