LEVEL package

Wafer-Scale Planarity Wafer-scale nonplanarities are not often well characterized in IC processing because their effect on yield is often low compared to other processing parameters however, work has been reported on its effects on electrical performance [99,100]. For the characterization of 3D integration and wafer-level packaging (WLP) approaches such as the use of redistribution layers, wafer-level planarization requirements have not been... 

Gutmann R, McMahon J, Rao S, Niklaus F, Lu J-Q. Wafer-level via-first 3D integration with hybrid-bonding of Cu/BCB redistribution layers. Proceedings of the International Wafer Level Packaging Congress 2005. 

First-Level Packages and Printed Circuit Boards... 

First-level packages provide interconnection between the printed circuit board and the chip. These packages must have the desired number of wiring layers, provide thermal expansion compatibility with the chip, provide a thermal path for heat dissipation from the chip, and keep electrical noise and transmission delay to the minimum. The two types of packages used are plastic packages and ceramic packages. 

The first-level packaging has to be defined carefully and in consideration of the full system, including test-and-trim requirements. Figure 5.8.1 illustrates the principle relations between standardization, cost, and flexibility. 

The manufacturing processes represent the link between the reliability issues of the microstructure on one hand and those of assembly and packaging on the other. The process flow must take into account, for example, the impact of the applied temperature range, pressure, and media on the sensor structure, which at the time of packaging is already completed. Dicing of sensor structures that include delicate elements, such as freestanding cantilevers or thin membranes, is usually very critical and requires some kind of protection which can be effectively provided by zero-level packaging on the wafer scale. 

Design and model the sensor function on the basis of a comprehensive set of model parameters (i.e., geometrical dimensions and material properties) and calculate tolerance bands for all layout-specific model parameters (including those for wafer-level packages) so that functional specs are safely met (see Section 4.1). 

Wafer bonding or cavity sealing is present on many MEMS products. Wafer-level packaging was first used in pressure sensors (Fig. 7.1.13a) to create an absolute... 

VTI g) the progression of automotive accelerometer packages produced by Motorola and h) inertial module-level packages from Bosch (courtesy Dr. Jiri Marek)... 

R. Islam, C. Rrubaker, P. Lindner, C. Schaefer. Wafer level packaging and 3-D interconnect for IC technology. In Proc. IEEE/SEMI Advanced Semiconductor Manufacturing Conf., 2002, pp. 212-217. 

On one side the development is based on thin film and micro-patterning technologies. Wafer level and foil processes used to produce high density interconnect electronic modules, and wafer level packaging was adapted to micro fuel cell development to achieve the required miniaturisation and cost reduction. By using reactive ion etching, high aspect ratio capillary structures of the anode and cathode side flow fields were achieved. 

We have deliberately included some information that goes well beyond what would normally be included in an introductory level packaging course, in order that it will be available for the more advanced student and for the practitioner. The Study Questions at the end of each chapter are intended to serve as review of the main concepts, and also to stimulate thought about aspects of plastics that have not been thoroughly covered. Answers to quantitative questions are provided in parentheses after the question. 

Briand et al. (2007) reported on a higher level integration of wafer-level packaged micromachined metal-oxide gas sensors. The concept was based... 

Chip on board wafer-level packaged metal-oxide gas sensors on printed circuit board. From Raible et al. (2006). 

Briand, D., Guillot, L., Raible, S., Kappler, J. and de Rooij, N. F. (2007), Highly integrated wafer level packaged MOX gas sensors , in Proceedings of the Transducers 07 conference, Lyon,France, June 10-14,2007,2401-4. 

Vardaman J. Sixth Annual International Wafer-Level Packaging Conf., Santa Clara CA ... 

---