Wafer-level packaging

Wafer-Scale Planarity Wafer-scale nonplanarities are not often well characterized in IC processing because their effect on yield is often low compared to other processing parameters however, work has been reported on its effects on electrical performance [99,100]. For the characterization of 3D integration and wafer-level packaging (WLP) approaches such as the use of redistribution layers, wafer-level planarization requirements have not been... 

Gutmann R, McMahon J, Rao S, Niklaus F, Lu J-Q. Wafer-level via-first 3D integration with hybrid-bonding of Cu/BCB redistribution layers. Proceedings of the International Wafer Level Packaging Congress 2005. 

Design and model the sensor function on the basis of a comprehensive set of model parameters (i.e., geometrical dimensions and material properties) and calculate tolerance bands for all layout-specific model parameters (including those for wafer-level packages) so that functional specs are safely met (see Section 4.1). 

Wafer bonding or cavity sealing is present on many MEMS products. Wafer-level packaging was first used in pressure sensors (Fig. 7.1.13a) to create an absolute... 

R. Islam, C. Rrubaker, P. Lindner, C. Schaefer. Wafer level packaging and 3-D interconnect for IC technology. In Proc. IEEE/SEMI Advanced Semiconductor Manufacturing Conf., 2002, pp. 212-217. 

On one side the development is based on thin film and micro-patterning technologies. Wafer level and foil processes used to produce high density interconnect electronic modules, and wafer level packaging was adapted to micro fuel cell development to achieve the required miniaturisation and cost reduction. By using reactive ion etching, high aspect ratio capillary structures of the anode and cathode side flow fields were achieved. 

Briand et al. (2007) reported on a higher level integration of wafer-level packaged micromachined metal-oxide gas sensors. The concept was based... 

Chip on board wafer-level packaged metal-oxide gas sensors on printed circuit board. From Raible et al. (2006). 

Briand, D., Guillot, L., Raible, S., Kappler, J. and de Rooij, N. F. (2007), Highly integrated wafer level packaged MOX gas sensors , in Proceedings of the Transducers 07 conference, Lyon,France, June 10-14,2007,2401-4. 

Vardaman J. Sixth Annual International Wafer-Level Packaging Conf., Santa Clara CA ... 

In packaging imaging sensors at the wafer level (Wafer Level Packaging), insulative adhesive in the shape of window firames are screen printed or otherwise simultaneously applied around all the devices on the wafer, a glass wafer is then attached, and the individual packaged die are singulated." ... 

Savastiouk S, Siniaguine O, Korczynski E. 3-D Stacked Wafer-Level Packaging. Advanced Packaging. Mar. 2000. 

Wang Q, Choa SH, Kim WB, Hwang IS, Ham SJ, Moon CY (2006) Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging. J Electron Mater 35(3) 425 32... 

As indicated in the previous sections, CMP has found many applications in the manufacturing of More than Moore devices. In this chapter, examples will be discussed where polishing processes have to be employed for the manufacturing of power devices, MEMS and MOEMS chips, and micro-displays. The described applications are exemplary and do not claim completeness. Wafer bonding will be covered with examples from the fields of stacked devices and wafer-level packaging (WLP), while TSVs will be treated in more depth in a separate chapter in this book. 

Wafer bonding is a technology to combine two substrates in order to achieve a mechanically stable connection between them. The technology is apphed for substrate production, for example, for the fabrication of silicon on insulator wafers or compound semiconductor wafers and for device fabrication, for example, for the fabrication of MEMS/MOEMS devices as described in previous sections, for stacking devices in 3D integration, or for wafer-level packaging. 

The benefits of wafer-level packaging can be summarized as follows ... 

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