Integrated-circuit device preparation

The need to be able to thin complex microelectronic devices, and to select and thin specific regions within them has resulted in ever-more sophisticated specimen preparation methods involving precision ion polishing. This requirement culminated in the development of the focused ion beam (FIB) technique, which is able to slice out electron-transparent foils from any multilayer, multiphase material with extreme precision. Overwijk et al. (1993) have described such a technique for producing cross-section TEM specimens from (e.g.) integrated circuits. 

The increasing importance of multilevel interconnection systems and surface passivation in integrated circuit fabrication has stimulated interest in polyimide films for application in silicon device processing both as multilevel insulators and overcoat layers. The ability of polyimide films to planarize stepped device geometries, as well as their thermal and chemical inertness have been previously reported, as have various physical and electrical parameters related to circuit stability and reliability in use (1, 3). This paper focuses on three aspects of the electrical conductivity of polyimide (PI) films prepared from Hitachi and DuPont resins, indicating implications of each conductivity component for device reliability. The three forms of polyimide conductivity considered here are bulk electronic ionic, associated with intentional sodium contamination and surface or interface conductance. 

Stability for use in optical interconnects. In the near future, optoelectronic integrated circuits and optoelectronic multichip modules will be produced. Materials with high thermal stability will thus become very important in providing compatibility with conventional 1C fabrication processes and in ensuring device reliability. Polyimides have excellent thermal stability so they are often used as electronic materials. Furuya et al. introduced polyimide as an optical interconnect material for the first time. Reuter et al. have applied polyimides to optical interconnects and have evaluated the fluorinated polyimides prepared from 6FDA and three diamines, ODA (3), 2,2-bis(3-aminophenyl) hexafluoropropane (3,3 -6F) (4), and 4,4 -6F (2), as optical waveguide materials. 

Although minimization in integrated circuits allows for faster device operation, propagation delays increase with increasing numbers of interconnects. To address this problem, lower dielectric constant materials have been prepared. 

A clean surface is essential for device reliability and performance [183], It becomes critical as the dimensions of devices become smaller and smaller as a result of ever-increasing integration and complexity. It has been estimated that over 50% of yield losses in integrated circuit (IC) fabrication are due to microcontamination [184], Today, a typical process flow for advanced ICs consists of 300 to 500 steps, 30% of which are wafer cleaning steps [185]. The need for wafer cleaning can be separated into three areas (1) preparation of the wafer surfaces for oxidation, diffusion, deposition, and... 

FETs are actually the basic building blocks of integrated circuits. To develop circuits using nanotubes, we first have to design nanotube-based transistors. Silicon nanowires represent one of the best characterized examples of semiconductor nanotubes with the structure, size, and electronic properties controlled reproducibly (Hu et al., 1999 Cui et al., 2001a). In particular, silicon nanowires can be prepared as single-crystal structures with controllable diameters as small as 2 to 3 nm (Cui et al., 2003 Wu, 2004). Both n- and p-type FET devices can be produced with well-defined and reproducible high-performance properties... 

Many specialised applications of magnetic materials involve the utilisation of ferrite thin films, such as magnetic and magnetooptic recording media, microwave devices in integrated circuits and coatings for microwave shielding. To prepare these ferrite thin fihns, a wide variety of techniques has been devised. 

Visible photoluminescence (PL) from porous silicon (PS) observed at room temperature has inspired sustained research into its potential application in Si-based optoelectronic devices and its theoretical basis (Canham 1990). This property is reviewed in the handbook chapter Photoluminescence of Porous Silicon. Most PS layers are prepared by anodic etching on/>-type Si substrates, a technique in which metal is often deposited on the rear surface of the Si substrate in order for it to be used as an ohmic back contact (see handbook chapter Porous Silicon Formation by Anodisation ). However, the requirement for a back contact electrode is a limitation of this method for example, it is difficult to form a PS layer on a sihcon-on-insulator (SOI) structure or on Si integrated circuits. A photoetching method, on the other hand, requires no electrodes and allows the formation of a visible luminescence layer on not only single-crystaUine Si substrates but also SOI structures. 

---