Floorplan

Fig. 1. Floorplan of the T-maze used. S, start box L, leg C, choice point D, sliding door A, arm and G, goalbox. Leg and arms 50 cm long.

A simplified flow for such a system exploration environment is shown in Fig. 2.6. For a given system configuration, a floorplanning tool could be used to extract related physical information. Then different feasibility analysis tools could be applied to evaluate the performance and cost of a given integration solution. Our cost analysis framework could be integrated to answer the what-if questions about the fabrication cost so that a cost efficient implementation could be identified. Of course, many other analysis engines are also required and we will further discuss these issues in the last chapter. 

We chose a scaled version of the HP-Compaq Alpha 21364 processor1191 in this research because of the availability of the design details and corresponding development tools (i.e. instruction simulator, cross compiler, and so on). The latest version of Alpha 21364 is built in a 0.18 pm process and has a die area of 397 mm2 We scaled the floorplan to a 0.13 pm process and the scaled version has a die area of 208 mm2. Figure 3.10 shows the floorplan of Alpha 21364 (the... 

Keywords 2.5-D integration, floorplanning, placement, routing, layout. 

In this research, we developed 2.5-D floorplanning, placement, and routing tools, which will be briefly introduced in the remaining sections. In Chapters 5 and 6, the details of our 2.5-D floorplanning and placement tools as well as the corresponding design case studies using the tools will be further covered in depth. 

Our 2.5-D floorplanning tool is based on a multi-layer Bounded Slice-Line (BSG) data structure. Basically, a BSG data structure is maintained for each layer of chip in a 2.5-D system and the legality of a floorplan solution inside each layer could be automatically guaranteed. The optimization is performed by a highly... 

In our 2.5-D layout design framework, we constructed a global router that could handle both monolithic and 2.5-D design implementations. After the floorplan design... 

The feasibility investigation is conducted at two major abstraction levels during physical design floorplan level (functional blocks) and placement (standard cells and macros) level. In the succeeding two chapters, we will discuss the feasibility at floorplan and placement levels, respectively. 

In the previous chapter, we briefly outlined our 2.5-D layout synthesis framework. In this chapter, the 2.5-D layout tools are applied on floorplan level designs. We will introduce our floorplanning algorithms along with the design case studies in this chapter. 

Under the 2.5/3-D integration context, the floorplanning problem can be formulated with different flavors according to the architecture of the designed system. Here we can classify VLSI system into three categories ... 

This formulation also applies to the situations where the footprint of inter-chip contacts is relatively big, e.g., 50 imx 50 pm (i.e. similar to that of flip-chip interconnection). Here inter-chip contacts should be considered as a coarsegrained resource and be assigned during the floorplanning stage. 

Besides traditional optimization objectives, a 3-D VLSI system implies a larger power density than its monolithic equivalent does. On-chip hot spots could incur serious degradations of system performance, power consumption, and reliability. However, we do observe that a 2.5/3-D floorplan without thermal constraints could lead to a maximum temperature of 180°C and a temperature gradient of 152°C[11] with traditional air-cooling techniques. Accordingly, it s of key importance to avoid excessive heat build-up and temperature difference in a 3-D integrated system. In other words, the thermal objective must be taken into account in the 3-D floorplanning problems formulated above. 

Let s first consider the 2.5-D floorplanning problem on Category 2 circuits. The problem is a simultaneous partition and assignment problem the input netlist has to be partitioned into multiple parts with each part assigned to a different chip in a 2.5-D system, and within the given chip every function block has to be placed without overlapping with other blocks. 

The optimization is accomplished through a simulated annealing engine with cost function given by Equation (5.1). The cost function is the weighted sum of three components total wire length, floorplan area, and total number of inter-chip contacts. 

With the concept of shadow block, we are able to extend our floorplanning algorithm to handle the second formulation of 2.5-D floorplanning problem. 

---