D Floorplanning

In a flattened design style, layout designers directly cany out the 2.5-D placement and routing tasks on a flatten netlist consisting of both standard cells and macros. Such a flow could usually accomplish superior solution quality, but at the cost of a longer turnaround time because of the inability to implement different blocks in parallel. 

In this research, we developed 2.5-D floorplanning, placement, and routing tools, which will be briefly introduced in the remaining sections. In Chapters 5 and 6, the details of our 2.5-D floorplanning and placement tools as well as the corresponding design case studies using the tools will be further covered in depth. 

5-D floorplanning tool is based on a multi-layer Bounded Slice-Line (BSG) data structure. Basically, a BSG data structure is maintained for each layer of chip in a 2.5-D system and the legality of a floorplan solution inside each layer could be automatically guaranteed. The optimization is performed by a highly 

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Besides traditional optimization objectives, a 3-D VLSI system implies a larger power density than its monolithic equivalent does. On-chip hot spots could incur serious degradations of system performance, power consumption, and reliability. However, we do observe that a 2.5/3-D floorplan without thermal constraints could lead to a maximum temperature of 180°C and a temperature gradient of 152°C[11] with traditional air-cooling techniques. Accordingly, it s of key importance to avoid excessive heat build-up and temperature difference in a 3-D integrated system. In other words, the thermal objective must be taken into account in the 3-D floorplanning problems formulated above. 

Let s first consider the 2.5-D floorplanning problem on Category 2 circuits. The problem is a simultaneous partition and assignment problem the input netlist has to be partitioned into multiple parts with each part assigned to a different chip in a 2.5-D system, and within the given chip every function block has to be placed without overlapping with other blocks. 

With the concept of shadow block, we are able to extend our floorplanning algorithm to handle the second formulation of 2.5-D floorplanning problem. 

Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning... 

We extended out 2.5-D floorplan design tool introduced in the previous sections to handle thermal effects. Initially, the 2.5-D/3-D floorplanning optimization is accomplished through a simulated annealing engine with a cost function defined as ... 

Table 5.4 3-D floorplans with and without thermal concern...

Our floorplanning tools could serve as the prototype for future 2.5-D system designs. A full-fledged 2.5-D floorplanning tool should be equipped with many new feature features described as follows. 

A Series of 2.5-D Physical Design Tools Due to the complexity of modem ASIC designs, automatic EDA tools are critical for a successful layout implementation. For 2.5-D integrated ASIC systems, additional complexity is introduced by the large amount of inter-chip communication resource. To be able to pack an ASIC system in a 2.5-D space, we developed 2.5-D floorplanning, placement and... 

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