D layout synthesis framework

In a flattened design style, layout designers directly cany out the 2.5-D placement and routing tasks on a flatten netlist consisting of both standard cells and macros. Such a flow could usually accomplish superior solution quality, but at the cost of a longer turnaround time because of the inability to implement different blocks in parallel. 

In this research, we developed 2.5-D floorplanning, placement, and routing tools, which will be briefly introduced in the remaining sections. In Chapters 5 and 6, the details of our 2.5-D floorplanning and placement tools as well as the corresponding design case studies using the tools will be further covered in depth. 

5-D floorplanning tool is based on a multi-layer Bounded Slice-Line (BSG) data structure. Basically, a BSG data structure is maintained for each layer of chip in a 2.5-D system and the legality of a floorplan solution inside each layer could be automatically guaranteed. The optimization is performed by a highly 

In our 2.5-D layout design framework, we constructed a global router that could handle both monolithic and 2.5-D design implementations. After the floorplan design 

In a 2.5-D layout, logic cells or macros could be placed on multiple device layers. From a routing point of view, however, the 2.5-D routing problem is almost identical to the monolithic routing problem. In fact, in today s typical monolithic designs, pins on a net could already be positioned on multiple metal layers. 

---

In the previous chapter, we briefly outlined our 2.5-D layout synthesis framework. In this chapter, the 2.5-D layout tools are applied on floorplan level designs. We will introduce our floorplanning algorithms along with the design case studies in this chapter. 

---