Thermal driven floorplanning

1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning 

A two chip-layer 3-D IC with a flip chip type package is shown in Fig. 5.5. As 

For the two vertically stacked dies, significant thermal gradients may exist due to non-uniform on-chip power distributions. To capture such non-uniform on-chip profiles, detailed thermal modeling and analysis is employed to achieve good accuracy. For this purpose, we adopt an efficient full-chip thermal simulator 231 that is based on detailed finite difference discretization of the following governing heat transfer partial differential equation 

To consider the temperature dependent leakage power consumption, it is desired to determine the transistor layer temperature distribution due to the power dissipated. For this purpose, the two transistor layers are laterally partitioned into M = 2 x N x N bins based on a user-specified granularity. Then, full-chip thermal simulation is applied to compute the average temperature increase in all bins if a unit power is dissipated in any of these bins. The power and temperature interactions for a particular power dissipating bin are illustrated in Fig. 5.6. A total of M x M interactions will be extracted at this stage such that for any given on-chip power dissipation distribution, the temperature increase at any of the two transistor layers can be determined by superposition at the specified granularity 23. Stated mathematically, we have 

It has been shown that for a given floorplan detailed full-chip thermal analysis can be employed to pre-characterize the interactions of the power dissipation and 

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Table 5.3 2.5-D thermal-driven floorplans with different weighting factors for...

Figure 5.11 Temperature snapshots of the thermal driven floorplanning with Benchmark AMI49. Both the maximum temperature and the temperature gradient are reduced during the optimization (see colour plate)...

J. Cong, J. Wei, Y. Zhang. A thermal-driven floorplanning algorithm for 3D Ics. Proceedings of International Conference on Computer-Aided Design, 2004, pp.306 - 313. 

Keywords 2.5-D integration, floorplanning, bounded-slice line, simulated annealing, temperature distribution, thermal-driven. 

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