D Thermal Driven Floorplanning Techniques

We extended out 2.5-D floorplan design tool introduced in the previous sections to handle thermal effects. Initially, the 2.5-D/3-D floorplanning optimization is accomplished through a simulated annealing engine with a cost function defined as  

Cost = A wirelength + y chip area + jj, num inter chip contacts (5.12) 

The cost function is the weighted sum of three components, total wire length, layout area, and total number of inter-chip contacts (i.e. interconnects between two chips). The three components have different implications the wire length has a different effect on the timing performance, the chip area is the major factor determining fabrication cost, and the number of inter-chip contacts affects the complexity of the 3-D fabrication process. In our implementation, we select A and y so that the first two terms can be roughly equal. Thus the floorplanner puts almost equal efforts to optimize wire length and chip area. The value of fi is chosen to reflect the relative cost , e.g., footprint, of inter-chip contacts. 

To consider the thermal effects, the cost function is extended by including another component, maximum on-chip temperature difference. The new cost function is as follows  

Cost = A wire length + y chip area + ii num inter - chip - contacts + [ max on - chip - temp - diff (5-13) 

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