Flip chip technology

The primary joining techniques used in MID technology are soldering for chips with solder bumps and, for chips with stud bumps, gluing with isotropic conductive adhesive (ICA), anisotropic conductive adhesive (ACA), or nonconductive adhesive (NCA) [81]. 

In soldering and when an ICA is used, the electrical connection is first established by the solder or the conductive adhesive before the bond is mechanically stabilized by application of an underfill. Using ACA or NCA makes it possible to combine electrical connection and mechanical stabilization in one process step. Electrically conductive connections made with nonconductive adhesives are based on mutual contact between the joining partners. A constant contacting force therefore has to be applied until the adhesive has cured. Contacting flip chips with adhesive 

FIGURE 5.21 Stud bump (left) and solder bumps applied by stenciling printing (right) 

FIGURE 5.22 Specimen process flow for flip-chip gluing with ICA [63] 

FIGURE 5.23 X-ray and metallographic images of flip chips mounted on MID substrates by gluing with NCA and soldering [63] 

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Semiconductor Packaging Cu Metallization and Flip-Chip Technology... 

Flip chip technology is a simple idea of flipping a chip to connect its device I/Os downside directly on the printed circuit boards. The apparent advantages are shorter electron pathways, increased number of I/Os per unit area for increased speed and power, cost reduction, and increased package density [1],... 

J.H. Lau, Flip Chip Technologies, McGraw-Hill, New York (1995). 

C.W. Argento, T. Flynn, and C. Demers, Next generation solder jetted wafer bumping for very fine pitch flip chip technology applications and beyond. Proceedings, IMAPS International Symposium on Microelectronics, Chicago, 1999, pp. 160-165. 

Fleischer, M., Ostrich, B., Rohle, R., Simon, E., Meixner, H., Bilger, C. and Daeche, F. (2001), Low-power gas sensors based on work-function measurement in low-cost hybrid flip-chip technology . Sensors and Actuators B Chemical, 80, 3,169-73. 

Kuleza FW, Estes RH. Solderless flip-chip technology. Hybrid Circuit Technol, Feb. 1992. 

Thin-film redistribution process using wafer-level passivation and cyclotene dielectric High-performance wafer-level CSP, JEDEC MSL 1 UltraCSP (Flip Chip Technology, Amkor and K S Flip Chip Division of Kulicke Sofia) EEPROM, Flash memory, DRAM, and standard electronic devices, PDAs, laptop PCs, disk drives, GPS, and MP3 players... 

Packaging (and Wire Bonding), Fig. 3 Flip-chip technology for electrical interconnection... 

ACA flip chip technology has been employed in many applications where flip chips are bonded to rigid chip carriers (13). This includes bare chip assembly of ASICs in transistor radios, personal digital assistants (PDAs), sensor chip in digital cameras, and memory chip in lap-top computers. In all the applications, the common feature is that ACA flip chip technology is used to assemble bare chips where the pitch is extremely fine, normally less than 120 /rm. For these fine applications, it is apparently the use of ACA flip chip instead of soldering which is more cost effective. 

A key factor in achieving a low cost, flip chip technology is the use of ICAs. In comparison to the classical flip chip technologies, the use of ICAs for the bumping and joining provide numerous advantages ... 

Fig. 14. Schematic depicting a flip chip technology utilizing chips with micromachined poljrmer bumps, (a) Process flow for creating micromachined polymer bumps in the wafer state, (b) Die attachment to a chip carrier.

Flip-chip technology, as shown in Fig. 11.14, is similar to TAB technology in that successive metal layers are deposited on the wafer, ending up with solder-plated bumps over the device contacts. One possible configuration utilizes an alloy of nickel and aluminum as an interface to the aluminum bonding pads. A thin film of pure nickel is plated over the Ni/Al, followed by copper and solder. The copper is plated to a thickness of about 0.0005 in., and the solder is plated to about 0.003 in. The solder is then reflowed to form a hemispherical bump. The devices are then mounted to the substrate face down by reflow solder methods. During reflow, the face of the device is prevented from contacting the substrate metallization by the copper bump. This process is sometimes referred to as the controlled collapse process. 

Flip-chip technology is the most space efficient of all of the packaging technologies, since no room outside the boundaries of the chip is required. Further, the contacts may be placed at any point on the chip, reducing the net area required and simplifying the interconnection pattern. 

Jitsuho, H. (Murata Manufacturing Co., Ltd.), Tatsuya, F., Akihiro, M., LTCC module using flip-chip technology for mobile equipment. Proceedings of SPIE — The International Society for Optical Engineering, Vol. 4587, 2001, pp. 283-286. 

Pohle R, Simon E, Fleischer M, Meixner H, Frerichs H-P, Lehmann M, Verhoeven H (2003) Realisation of a new sensor concept improved CCFET and SGFET type gas sensors in hybrid flip-chip technology. In Proceedings of the 12th international conference on solid-state sensors, actuators and microsystems, TRANSDUCERS 2003, June, pp 135-138... 

K. N. Tu, K. Zeng, Tin-lead (Sn-Pb) solder reaction in flip chip technology. Mater. Sci. 

Figure 31 Structure of IBM s solder bumps fabricated at the wafer scale before integrated circuits are connected to wiring boards by the flip chip technology (a) integrated circuit with an area array of solder bumps (b) exploded view showing the bump structure with silicon substrate 1, aluminium bonding pad 2, silicon dioxide 3, silicon nitride passivation 4, titanium-tungsten alloy 5, sputtered copper 6, plated copper 7, and reflowed plated...

To reduce the cost of flip chip interconnection, an organic process was developed at Epoxy Technology Inc. [81]. The polymer flip chip technology (PFc ) a polymer dielectric paste and an electrically conductive adhesive. 

Figure 48 Stress analysis model for tri-material assemblies (a) completely filled joint representative of backside die attachment (b) bonding technique using small dots of adhesive as in flip chip technology.

Basically, two elastic layers denoted by the subscripts 1 and 3 are bonded by either a completely filled joint (Fig. 48(a)) or small dots of adhesive as in flip chip technology (Fig. 48(b)), both being denoted by the subscript 2. The three layers have uniform thicknesses hi, /12, elastic moduli Ei, E2, 3, shear moduli Gi, G2, G3, Poisson s ratios Vi, V2, V3, and coefficients of linear thermal expansion ai, a2, a3. The other parameters are the die half-length /, the distance from the centre of the die x, and the temperature differential AT between the zero-stress temperature Tq and the operating temperature T. The model proposed by Chen and Nelson demonstrates that the shear stress generated by the temperature differential is given by... 

Estes, R. H., Kulesza, F. W. (1995). Conductive adhesive polymer materials in flip chip applications. In J. H. Lau (Ed.), Flip chip technologies (pp. 223-267). McGraw Hill, New York. 

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