Wafer bumping

Hayes, D. Wallace, D. 1998. Solder jet printing Wafer bumping and CSP applications. Chip Scale Review 2 75-80. 

Figure 11-19. Pb-free wafer bumping with 85-pm bumps printed on-the-fly top) and in profile bottom)...

C.W. Argento, T. Flynn, and C. Demers, Next generation solder jetted wafer bumping for very fine pitch flip chip technology applications and beyond. Proceedings, IMAPS International Symposium on Microelectronics, Chicago, 1999, pp. 160-165. 

Micronox MX2301/ Kyzen Semi-aqueous blend Defluxing semiconductor wafer bumps in flip-chip, chip scale, and micro BGA applications 191-195 N/A 25-35 82 N/A... 

Other electrical interconnection techniques such as wafer bumping and flip-chip bonding have emerged [13]. As shown in Fig. 3 (courtesy of Amkor Technology, Inc.), small metal balls... 

Copper is another candidate material for wafer bumping. Compared to gold, copper costs less but has a good electrical and heat-dissipating performance due to its low electrical resistivity and high thermal conductivity. 

Other electric interconnection techniques such as wafer bumping and flip-chip bonding have emerged [11]. As shown in Fig. 3 (Courtesy of Amkor Technology, Inc.), small metal balls (Ag/Sn or Sn/Pb) are directly electroplated on the metal pads of the device chip. The chips are then flipped over and bonded to a printed circuit board (PCB) or a substrate with prefabricated metal connections. An epoxy underflll is then used to fill the space... 

Figure 4. Simplified schematic of an optical/infrared focal plane array. The detector is a thin wafer of light sensitive material that is connected to a thin layer of solid state electronics - the connection is made either by direct deposition (CCD) or bump bonding (IR detector). The solid state electronics amplify and read out the charge produced by the incident light.

Figure 20 AFM image of a Si wafer used in the fluorescence measurements. No bumps or pits expected from the light-scattering images were observed in the high-resolution (500 x 500 nm2) scanning. (B) The cross section of the horizontal line in (A). (From Ref. 16.)...

Two challenges are uniform thinning of the top wafer and high aspect ratio etching of the thinned layer. An approach to high-density TSV interconnection using a variety of CMOS-compatible fabrication steps (such as CVD tungsten and polysilicon, BCD copper, and solder micro-bumps) is presented by Knickerbocker et al. in References 86 and 87. 

Fig. 14.3 Process steps involved in the C4NP technology. Wafers with BLM and solder-fiUed molds are processed in parallel and joined together. Solder bumps are thus transferred to the wafer. Inset Solder balls formed by C4NP process. Ref. [23] reproduced with permission of the Electrochemical Society...

The majority of substrates consisted of 200 nm of Au vapor deposited on Si( 100) wafers, with a 10 nm Ti adhesion layer between the Si and Au. They appear mirror like to the eye. but consist of 40 nm hemispherical bumps. Recently, the Au on Si has been replaced with Au on glass, as it can be flame annealed prior to use. This results in cleaner substrates, as well as substrates with more atomically flat regions. 

Alternate approaches that eUminate the capillary-flow underfill process currently used by electronics assemblers, involve pushing the problem back to the wafer stage. One process, wafer-level underfill (WLU) (Figure 5.12), consists of applying the underfill material to a bumped wafer and then B-staging the underfill. The wafer is then diced and the die are positioned on corresponding connection pads on an interconnect... 

In a similar process, known as polymer-film interconnect (PFI), an insulative thermoplastic film is laminated over the devices at the wafer stage, and vias are opened over the bonding pads using a laser. At that point, either the normal solder bumps can be formed or a silver-filled conductive adhesive can be stencil printed into the vias to form polymer bumps. After printing, the epoxy is B-staged and the flip-chip devices are diced. In assembly, the devices are heated to a temperature that completes the cure of the B-staged bumps and simultaneously reflows the thermoplastic underfill material. 

Once the epoxy bumps have been formed, the wafer is thinned from the backside, the devices are singulated, and their edges beveled at 45° to expose gold pads at the periphery of die. The chips are then stacked and bonded with thermally conductive, electrically insulative epoxy (Figure 5.16). Paste adhesives are cost effective and can be dispensed with existing epoxy dispensing equipment. However, with... 

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