Contact electrization 272 Diffusion barrier

Interconnect. Three-dimensional structures require interconnections between the various levels. This is achieved by small, high aspect-ratio holes that provide electrical contact. These holes include the contact fills which connect the semiconductor silicon area of the device to the first-level metal, and the via holes which connect the first level metal to the second and subsequent metal levels (see Fig. 13.1). The interconnect presents a major fabrication challenge since these high-aspect holes, which may be as small as 0.25 im across, must be completely filled with a diffusion barrier material (such as CVD titanium nitride) and a conductor metal such as CVD tungsten. The ability to fill the interconnects is a major factor in selecting a thin-film deposition process. 

In order to establish good electrical contact to the sensitive layer, it was necessary to coat the electrodes with a metal stack of Ti/W (diffusion barrier and adhesion layer) and Pt. The usage of a shadow mask during the metal deposition ensures full compatibility with other MEMS processing steps so that it is possible to fabricate various CMOS-MEMS devices on the same wafer. 

Examples are source, drain, and gate metallization in transistors and diffusion barriers, ohmic contacts, and interconnections (lines, vias, plugs) in integrated circuits. The favorable electrical, mechanical, and chemical properties are ... 

Another strategy is to make use of electrically conducting porous diffusion barrier layers (DBLs) coated on the surface of the alloy in order to suppress metal element diffusion between the electrode and the substrate (Fig. 8b). Manufacturability of these layers is easier to achieve. The challenges are to make the layers porous enough to ensure gas transport from the metal substrate towards the anode and to cover aU contact points between electrode particles and substrate particles for efficient inhibition of mass transport [14, 15]. 

Another problem in the construction of these devices, is that materials which do not play a direct part in the operation of the microchip must be introduced to ensure electrical contact between the electronic components, and to reduce the possibility of chemical interactions between the device components. The introduction of such materials usually requires an annealing phase in the construction of the device at a temperature as high as 600 K. As a result it is also most probable, especially in the case of the aluminium-silicon interface, that thin films of oxide exist between the various deposited films. Such a layer will act as a barrier to inter-diffusion between the layers, and the transport of atoms from one layer to the next will be less than would be indicated by the chemical potential driving force. At pinholes in the A1203 layer, aluminium metal can reduce Si02 at isolated spots, and form the pits into the silicon which were observed in early devices. The introduction of a thin layer of platinum silicide between the silicon and aluminium layers reduces the pit formation. However, aluminium has a strong affinity for platinum, and so a layer of chromium is placed between the silicide and aluminium to reduce the invasive interaction of aluminium. 

Studies of the electrical characteristics of Au contacts on InP(llO) (45), GaAs(llO) (45), CdS(1010) (46), and CdSe(lOlO) (46) confirm the expectations based on the insight gleaned from our examination of replacement reactions on GaAs(llO). The presence of a few monolayers of reactive metal (e.g., A1 or Ni) prior to deposition of the Au suppresses the diffusion of the semiconductor species through the Au overlayer and reduces the asymmetry of the I-V characteristic of the Schottky barrier, making it more "ohmic". Indeed, a few monolayers of A1 on CdSe(lOlO) renders the resulting Au/Al/CdSe composite contact completely ohmic (46). Thus, studies of semiconductor-metal interface structure in this case led to a new technique for... 

In order to describe the stability of fine disperse systems stabilized by diffuse ionic layers, one has to use the total free energy of interaction between particles, instead of the energy per unit film area, and compare the barrier height,, to the thermal energy, kT. For us to be able to use the solution derived for the case of plane-parallel surfaces, let us introduce some effective area of particle contact, Se[. Then the potential barrier height for the particles can be expressed as = A5 max St(. When diffuse part of electrical double... 

The mean number ElEj of electron - hole pairs generated in semiconductors— with a mean formation energy of , = 3.6eV in silicon, for example—normally recombine. The electric field inside depletion layers separates the charge carriers, and minority carriers can diffuse to the depletion layer and contribute to the charge collection /eg or electron-beam induced current. Depletion layers can be formed by p-n junctions parallel or perpendicular to the surface or by Schottky barriers formed by a nonohmic evaporated metal contact. Therefore, a scanning electron probe becomes a useful tool for qualitative and quantitative analysis of junctions and semiconductor parameters [227], which is demonstrated by the following examples ... 

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