Circuit Board Faults

The framework presented in Table 3 suggests a linear sequence of functions, but in practice there are some branches and reentries in the sequence. For example, an indication of one type may be located, a decision made, and action taken without consideration of any other indications. This occurs when a discrete fault with major consequences is located, such as a missing chip on a circuit board. For simplicity, this treatment will consider only sequential steps. 

The raw materials, which comprise electronic components and printed circuit boards, are cleaned. Various metal and plastic parts are plated, moulded, trimmed and printed. Workers then assemble the parts and components using screws or clips, by soldering or with the use of adhesives. The assembled product is usually a functional unit. This is tested and any fault rectified. The functional units are assembled into the final... 

For electrical test purposes, faults may be defined as test system measurement results other than those programmed to be representative of a good board. The faults detected may or may not impact the functionality of the circuit board, though in most cases they wiU. Some guidelines... 

The fault tree development proceeds in this manner until all output board failures that can affect the output contact of Interest are analyzed, and one of the Intermediate events is "Signal from the data bus on the motherboard incorrect". A manner in which this can occur is the existence of faults in those components on the CPU and other I/O circuit boards that are directly connected to the motherboard. The other mechanism is that the data signal to the motherboard from the CPU board is Incorrect, which then entails an analysis of the CPU board. 

Fault diagnosis method for circuit board based on BP neural networks... 

The remainder of this paper mainly focuses on the fault detection model of the electronic products containing instant faults (i.e. hard faults), and take the environmental changes and external stresses into consideration. The fault and false alarm model is introduced and a type of BIT circuit adopting an adaptive threshold is developed. The hardware implementations are discussed in this paper according to the designing requirements, and a printed circuit board is also made for test and verification. 

The background knowledge and working principles are discussed. The circuit design implementations are also presented in this paper. A hardware BIT circuit board monitoring a typical fault mode is manufactured. Finally, the experimental analysis show that the BIT using adaptive detection... 

It should be realized that transistor testers are available on the market (References PORTABLE TRANSISTOR TESTER MODEL 510 FOR IN-CIRCUIT TESTS, BK PRECISION). They usually can be directly applied Co Che transistor to be tested without removing it from the printed circuit board. If such a fixture is available, then you may immediately make clear whether the fault in your circuit depends on the transistor or not. If it does, you simply replace the transistor and check whether the circuit works or not. If it does not work, then in any case you must disconnect Che transistor and check (K3, R4) and (Rl, R2). 

If the circuit had previously undergone dc analysis and was found to operate correctly dc-wise, then the present fault, that Is, open signal path between Input and output, may depend on an open C capacitor or on an Interrupted connection In series with C on the printed-circuit board. 

Consider now the following amplifier, whose nominal gain should be 10, but actually is found to be 1 (Fig. 6.17). The fault may depend on Rl open-circuited or R2 short-circuited. Open and short circuit may be related to faults on the printed circuit board. In this case visual inspection aiming at detecting possible Interruptions, accidentally disconnected components, or stray jumpers has to be carried out first. If nothing comes out of this inspection, measure the resistors Rl and R2 and change the defective one(s). Remember that there is still the possibility of a gain in the operational amplifier much below the nominal value, in which case it has to be replaced. 

In a computerized plant, it is best to avoid putting redundant inputs on or in the same slot, cluster, or board in the computer. The safety system should be continuously exercised. An independent safety system suffers from a major drawback, particularly if it is implemented using relays. This drawback is that the safety system usually remains inert for long periods of time. Electronic circuits or relays are subject to failures such that when the safety system is called on to operate, it may be incapable of doing so. The best way to ensure that the safety system has not suffered a fault is to continuously exercise it. This is best done if the safety system is also responsible for control calculations and is constantly in use (Wensley, 1986). 

We injected 2,944,640 faults in the AUT of the FPGA board running a 6 x 6 matrix multiplication protected with OCFCM, VAR and BRA. From those faults, 54,024 caused an error in the circuit s output when considering no farrlt tolerance detection. Since the fault injection was exhaustive, we can asstrme that, except for placement and routing differences, the microprocessor core has 54,024 sensitive bits, which represents 1.8% of the injected faults. This represents a proportion of 54 bit-flips in the configuration memory bits to cause a functional error in the design. 

This economical test exposes die climatically unstable points of electronic components. Due to the nature of the test, the entire board is evaluated. This test accelerates the mechanisms of electrochemical migration. Consequently, faults that previously would appear after months or even years can be detected during the development process. To identify potential weak points, the assembly is operated in standby mode and immersed in deionized water. Testing while the assembly is in full operation is even more effective. The sensitivity of the circuit to moisture exposure is assessed on the basis of flie recorded test current, combined with a subsequent examination of the assembly. Through weak point analysis, a Yes/No decision can be determined concerning the expected service life, of the assembly. 

Based on the results of the PHA, recommendations made by 30% review boards, and guidance provided in the system safety program plan, detailed hazard analyses are made of specified (critical) subsystems. The techniques for these SSHAs are as outlined in the system safety program plan or as selected by the SSWG. Failure modes and effects analysis (FMEA) and/or fault tree analysis (FTA) are generally the techniques of choice. Software hazard analysis, common cause analysis, and/or sneak circuit analysis may also be appropriate. 

In a split-board consumer unit, about half of the total number of final circuits are protected by the RCD. A fault on any one final circuit will trip out all of the RCD protected circuits, which may cause inconvenience. 

The computer system of the station control and data acquisition is a distributed micro processer based systems. A digital multiplexed control system takes the place of hard wired analogue control. This accounts for a significant reduction in cable usage. Built-in diagnostics and board level maintenance makes restoration of operability of any fault in the system a matter of replacement of printed circuit cards. Automatic control systems and procedures are deployed to simplify these procedures and power level manoeuvers. In case of unsafe conditions the reactor protection system (PMS) takes over and automatically scrams the reactor and actuates the relevant safety systems. Diverse methods are used to assure the shutdown of the reactor in hypothetical situations. The systems also provide for post-accident monitoring. 

Guided diagnostics can be used on certain types of hardware to facilitate semi-automated circuit testing. The test connector typically taps into one of the system board input/output ports and, armed with the proper software, the instrument goes through a step-by-step test routine that exercises the computer circuits. When the system encounters a fault condition, it outputs an appropriate message. 

Guided-fault isolation (GFI) is practical with an emulative tester because the instrument maintains control over the entire system. Automated tests can isolate faults to the node level. AU board information and test procedures are resident within the emulative test instrument, including prompts to the operator on what to do next. Using the microprocessor test connection combined with movable probes or clips allows a closed loop test of virtually any part of a circuit. Input/output capabiUties of emulative testers range from single point probes to weU over a hundred I/O Unes. These lines can provide stimulus as weU as measurement capabilities. 

An observed fault is not always a reliable pointer to a defect. For example, if an IC loaded onto a board has defective solder on one input pin causing an open circuit, this may appear to the IC to be a permanent, stuck-at-1 fault on that input.This faulty behavior may not be readily... 

Care should be taken in the design of systems such that critical circuits are not used with series-rated systems. In the case of our 200,000-AIC main, if there were a high current fault at a downstream sight, the 100,000-AIC circuit breaker would interrupt and it would also cause the 200,000-AIC main circuit breaker to interrupt simultaneously, which would terminate power to the entire distribution system. If this were used in, say, a hospital, you would not want a short circuit in a panel board or a downstream distribution switchboard to also cause the main circuit breaker to trip, taking aU power out of the hospital. In those types of critical situations, the minimum circuit breaker AIC rating should be no less than the available system fault current delivered by the utility. 

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