Chip-on-substrate

The assembly of uncased or bare chips on substrates has become popular mostly due to the ability of such assembhes to reduce the area of interconnections.The ideal limit for such assembly would be to place all the chips tightly together, without any space in between. This would result in 100 percent packaging efficiency, a metric measuring the ratio of silicon area to the substrate area. Naturally, such 100 percent efficiency is not achievable, but this metric is still useful in ranking various substrate construction or bare chip attachment methods, as shown in Rg. 2.8. 

Horvath, R. Pedersen, H. C. Skivesen, N. Svanberg, C. Larsen, N. B., Fabrication of reverse symmetry polymer waveguide sensor chips on nanoporous substrates using dip floating,... 

The above concept of forming adhesive bonds in the solid state has been used to demonstrate the possibility of the parallel processing of a multi-chip module substrate, consisting of a multilayered polymer substrate with circuitry embedded on each polymer layer via lithographic processing [43], In this case, it is essential that the polymeric layer retains its dimensional stability so that registration and interconnections between the layers can be achieved using a Pb-Sn solder (see Fig. 28). A copolyester which appears to be ideally suited for this purpose is the 4/1 PHBA/BPT which melts at 320 °C in the randomized form... 

As an example of Si technology, Figure 1 illustrates a packaged 1-megabit dynamic-random-access-memory (DRAM) chip on a 150-mm-diameter Si substrate containing fabricated chips. Each of the chips will be cut from the wafer, tested, and packaged like the chip shown on top of the wafer. The chip is based on a l- xm minimum feature size and contains 2,178,784 active devices. It can store 1,048,516 bits of information, which corresponds to approximately 100 typewritten pages. 

The objective of the 2.5-D placement problem is to map a cell netlist (pure standard cell or mixed macro/standard cell) to unique positions in a layered space as illustrated in Fig. 6.1. The inter-chip contacts are assumed to be placed on top of the chip with no need to consume substrate area. We need to differentiate two scenarios hierarchical and flattened design styles. In a hierarchical design set up, after the floorplanning step, cells in a block need to be placed. As mentioned in the last chapter, a random-logic based block could be split into two chips. The 2.5-D placement problem is to assign the cells within such a block to unique positions on two chips. On the other hand, in a flattened design style, the 2.5-D placement problem is to place both standard cell macros onto stacked chips. 

Bare die and other chip devices are attached with electrically conductive or nonconductive adhesives to ceramic substrates having defined circuit patterns produced by thin-film vapor deposition and photoetching of metals or by screen-printing and firing of thick-film pastes. With recent advancements in fine-line printed-circuit boards, adhesives are also finding use in attaching bare die to PWBs, a technology known as chip-on-board (COB). 

Chip-on-flex is similar to chip-on-board except that the die, chips, or CSPs are wire bonded, flip chip attached, or epoxy connected to a flexible circuit instead of to a rigid interconnect substrate such as a PWB. 

Kwon W, Yim M, Paik K, Ham S, Lee S. Thermal cycling reliability and delamination of anisotropic conductive adhesives flip chip on organic substrates with emphasis on thermal deformation. Trans ASME (Jun) 2005 Vol. 127 86-90. 

Assembly of silicon chips onto substrates with anisotropically conductive adhesives uses specialized equipment, initially developed for ffip-chip solder and TAB inner lead bonding. Heat and pressure are transmitted to the adhesive through a thermode attached to a robotic arm or a high-precision linear translator. Equipment requirements are more demanding than for solder assembly, as no self-alignment can occur. A minimum placement accuracy of 0.0005 in. is required. Coplanarity between the substrate and die is critical one study reports maintaining coplanarity to within 0.00004 in. [19]. The pressure required to achieve interconnection depends on the size of the die, the type of conductive particle used, and the viscosity of the adhesive at the bonding temperature. 

Stacked chips on rigid substrate Chip scale packaging efficiency integrating multiple functionality and high silicon density Thin profile fine pitch BGA (TFBGA), low profile fine pitch BGA (LFBGA) (Orient Semiconductor Electronics USA) Portable electronics requiring flash memory, SRAMs, DRAMs, and controller chips... 

The development of microfluidics-based Lab-on-Chip devices involves the incorporation of many of the necessary components and functionality of a typical laboratory onto a small chip-sized substrate. When experiments are carried out in a Lab-on-Qiip, forces are needed to drive liquids to flow through microchannels. Microfluidic flows are readily manipulated using many kinds of external field (pressure, electric, magnetic, capillary, and so on). As the dimensions shrink, the importance of surface forces relative to volume forces increases. Such... 

The transposition of capillary electrophoresis (CE) methods from conventional capillaries to channels on planar chip substrates is an emergent separation science that has attracted widespread attention from analysts in many fields. Owing to the miniaturization of the separation format, CE-like separations on a chip typically offer shorter analysis times and lower reagent consumption augmented by the potential for portability of analytical instrumentation. Microchip (p-chip) electrophoresis substrates boast optically flat surfaces, short diffusion distances, low Reynolds numbers, and high surface (or interface)-to-volume ratios. By exploiting these physical advantages of the chip over conventional capillaries, efficient p-chip electrophoresis systems can accomplish multiple complicated tasks that may not be realized by a conventional CE system alone. 

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