Packaging efficiency

R. Lilienfeld, A Study of Packaging Efficiency as It Relates to Waste Prevention, The Cygnus Group, Ann Arbor MI, March 1995. 

The property gap that exists between HDPE and LDPE has been filled by LLDPE. This polymer can be prepared by solution- or gas-phase polymerization, and is actually a copolymer of ethylene with 8 to 10% of an a-olefin, such as but-1-ene, pent-l-ene, hex-l-ene, or oct-l-ene. This produces a chain with a controlled number of short-chain branches and densities intermediate between HDPE and LDPE, thereby allowing it to be prepared in various grades by controlling the type of the comonomer. Thus, the use of oct-l-ene gives a lower-density product than that obtained when but-l-ene is incorporated in the chain because the longer (hexyl) branch in the former pushes the chains further apart than the ethyl branch of the latter, hence lowering the packaging efficiency of the chains. 

Stacked chips on rigid substrate Chip scale packaging efficiency integrating multiple functionality and high silicon density Thin profile fine pitch BGA (TFBGA), low profile fine pitch BGA (LFBGA) (Orient Semiconductor Electronics USA) Portable electronics requiring flash memory, SRAMs, DRAMs, and controller chips... 

Flex substrate, die up and wire bonded configuration, overmolded Near CSP packaging efficiency exBGA (Amkor) Portable electronics (cell, pagers) and digital cameras and PCs/disk drives... 

In general, the current PWB technology is adequate to provide direct chip terminations if wire-bonding or TAB techniques are used for interconnecting bare chips to the substrate. It requires placing suitable bonding pads spaced by the required pitch in one or two rows around the chip site. While this somewhat reduces the packaging efficiency of the board, it is stiU an effective method for DCA assemblies. 

The assembly of uncased or bare chips on substrates has become popular mostly due to the ability of such assembhes to reduce the area of interconnections.The ideal limit for such assembly would be to place all the chips tightly together, without any space in between. This would result in 100 percent packaging efficiency, a metric measuring the ratio of silicon area to the substrate area. Naturally, such 100 percent efficiency is not achievable, but this metric is still useful in ranking various substrate construction or bare chip attachment methods, as shown in Rg. 2.8. 

FIGURE 2.8 Packaging efficiency. (Courtesy ofBPA, used with permission.)... 

Packaging efficiency of 100 percent is impossible to achieve because all chip-mounting methods require some space around the chips. Even with flip-chips, there must be a distance left between the chips to permit room for the placement tool. 

FIGURE 4.1 Evolution of system-level packaging efficiency. 

Because the cathode material is also the electrolyte, the packaging efficiency will be much higher than for solid cathodes. 

Modidar packaging efficiency Good Excellent Good... 

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