Minimum feature size

The MOSFET, the most important microelectronic device, can be reduced in dimension to reach a minimum feature size of 0.1 micron but even lower dimensions (0.05 microns) are foreseen, as demonstrated by recent advanced experiments. 

Graphical representation of the minimum feature size vs. year of commercialization for MOS devices. 

The 193 nm light from a Questek ArF excimer laser was used to obtain sensitivity data by exposing 1 cm2 areas. Fine line patterning with 193 nm light was done on a Leitz IMS exposure apparatus with either 15X or 36X reflective objectives. The fluence was varied from 0.1 to 100 mJ/cm2/pulse. All exposures at 248 nm were conducted on a deep-UV stepper(12) with a NA = 0.38 lens, 5X reduction, a minimum feature size of 0.4 pm and a fluence of -0.3 mJ/cm2/pulse. 

Figure 1. Minimum feature size on a MOS random access memory device as a function of the year the devices were first commercially available.

There is a variety of exposure technologies, each with a fundamental resolution limit resulting from radiation interactions with both the hardware and the resist. From a practical standpoint, factors such as alignment tolerance and resist swelling usually degrade resolution to a point where minimum feature sizes are larger than theoretically expected. Nevertheless, examining the fundamental resolution limits of the various techniques can be instructive. 

C Linewidth Control, This parameter refers to the necessity of maintaining the correct features size across an entire substrate and from one substrate to another. This is important since the successful performance of most devices depends upon control of the size of critical structures, as for example in the gate electrode structure in an MOS device. As feature size is decreased and circuit elements packed closer together, the margin of error on feature size control is reduced. The allowable size variation on structures is generally a fixed fraction of the nominal feature size. A rule of thumb is that the dimensions must be controlled to tolerances of at least 1/5 the minimum feature size. Linewidth control is affected by a variety of parame-... 

Depth of field depends on substrate reflectivity, the degree of partial coherence and the minimum feature size (5). In practice, however, the classical depth of field for the incoherent case (X-f2(N.A.)2) gives a reasonable approximation. Two layer resist processes in which the image is formed in a thin, flat, resist layer on top of a much thicker planarizing layer, alleviate the need for a large depth of field and make it easier to form high resolution, high aspect ratio, resist patterns (6,7). Satisfactory results can be obtained at contrast levels as low as 40%. 

Figure 2. Minimum feature size on MOS random access memory devices as a function of year of commercial availability. (Reproduced with premission...

Limitations. The number of transistors present on a chip lias doubled approximately every 18 months since the integrated circuit was first developed. The main reason for this continuing decrease in the minimum feature sizes of transistors (and consequent increase in density of transistors on the chip) has been the development of photolithography. The most important limitation for further size reduction remains the development of new photo- and utlier lilliugraphic techniques. 

Most microelectronic facilities can readily achieve minimum feature sizes on the order of 10 pm or better. State-of-the art facilities can produce devices with feature sizes of a few tenths of a micrometer. The lower limit is still decreasing, but the effort required expands exponentially as feature size decreases. Frequently, large numbers of devices can be simultaneously fabricated on the same substrate and subsequently separated by scoring and breaking or sawing the substrate after all processing steps are complete. While complex multilayer devices are possible, most film electrode devices reported to date involve only one or two layers. 

Fig. 2. Improvement over time (a) chip area and minimum feature size (b) maximum speed and cost per logic gate.

As an example of Si technology, Figure 1 illustrates a packaged 1-megabit dynamic-random-access-memory (DRAM) chip on a 150-mm-diameter Si substrate containing fabricated chips. Each of the chips will be cut from the wafer, tested, and packaged like the chip shown on top of the wafer. The chip is based on a l- xm minimum feature size and contains 2,178,784 active devices. It can store 1,048,516 bits of information, which corresponds to approximately 100 typewritten pages. 

Figure 3. Components per silicon chip versus calendar year. Segments A and B are history segments CDG and CEF are projections based upon 0.5- and 0.25-[Lm minimum feature sizes, respectively. (Reproduced with permission from reference 4. Copyright 1984 IEEE.)...

Figure 4. Trend in minimum feature size on silicon integrated circuits versus year of circuit introduction. Markers (o) give an indication of relative feature...

In equation 1, bmin is the minimum feature size transferable, A is the wavelength of light, s is the separation between the mask and the substrate, and d is the thickness of the resist layer. In projection printing, a series of undulating maxima and minima are produced. Because of mutual interference, the dark region is never completely dark, and the maximum brightness does not correspond to 100% transmission. The quality of transfer can be conveniently indicated by the modulation index, M, which is defined as follows ... 

In equation 3, W is the minimum feature size, k is an empirically determined constant that depends on resist processing, A is the wavelength of the incident... 

Feature Sizes. Although minimum feature sizes in TFML interconnections are large relative to IC feature sizes (i.e., 25- xm versus l- xm line widths), the conductor and dielectric layers are substantially thicker in TFML structures, a fact that results in high aspect ratios. Conductor layers must be several micrometers thick to keep resistive losses low, and dielectric layers must be 10 to 30 xm thick to maintain low interconnection capacitance. Thus a thickness width aspect ratio as large as 1 1 is frequently required. This aspect ratio demands anisotropic-etching processes. 

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