Bonding pads thickness

The last technique commonly employed to deposit metals for compound semiconductors is electroplating (150). This technique is usually used where very thick metal layers are desired for very low resistance interconnects or for thick wire bond pads. Another common use of this technique is in the formation of air-bridged interconnects (150), which are popular for high speed electronic and optoelectronic circuits. 

With use of a passivation layer 29 a further embodiment allows for utilization of thin metal layers for both the first metal layer 18 and the second metal layer 20 to optimize yield and desired characteristics for the rows 21 and columns 22. The desired thickness of the bonding pads 30 and 31 being built up by a subsequent metal deposition. This is achieved by patterning the passivation layer 29 with a mask to form column bonding pad vias 32 and row bonding pad... 

Each detector 14 includes a detector crystal region 21 having a junction 22 which is connected to an indium bump 23. The indium bump bonds to the bonding pad 80 which is, in turn, bonded to a metallized trace 13. The sensitive area plane 12 is parallel to the plane formed by the edge of the supporting substrate and the multilayer thick/thin film interconnect pattern 50. 

In this mode of operation, ECMP leaves a uniform Cu film across pattern densities and allows conventional CMP to operate at low pressures less than 2 psi. The remaining Cu film after ECMP is measured by the focus ion beam (FIB) technique [25]. The film thickness is quite uniform across the wafer regardless of the pattern structures. For example, the thickness of the film over some representative structures (0.18-pm array, 0.25-pm array, 10-pm line, and 50-pm bond pad) is within a range of 200 A or less, as seen in Fig. 11.16. 

Zinc pretreatment baths are prepared by varying the amount of zinc oxide in a strong alkaline bath. A commercial zincation bath is also analyzed for the purpose of comparison. Three different types of substrates are used CMOS wafer chips with multiple Al bond pads, sputtered silicon wafers, and silicon wafers coated with e-beam evaporated Al. Morphologies of the 3 types of substrates vary in terms of grain size and roughness (Fig. 2). Thickness of the Al films ranges from 5000 A to 1 pm. 

Thin gold or aluminum wire, with a diameter of 0.025-0.075 mm, is used to make a connection between the bonding pad and the sensor. This wire bonding is performed using standard microelectronic techniques such as thermal compression or ultrasound bonding. The external lead wire is then bonded onto the bonding pad. Because of the thinness of the metallic film of the pad, the external lead wire connection is usually made by thermal compression. Similar to the connection of the thick-film sensor, the conductive epoxy is first applied to the connecting joint and then covered with insulation epoxy or silicone. 

Protective Chip Pad Layer. As with virtually all flip chip processes, the A1 bond pads must be protected to eliminate the formation of nonconductive aluminum oxide. This ensures a low and stable resistance at bond-bond pad interface. The PFC process utilizes an electroless plating technique, using Ni/Au or Pd, to cover the A1 bond pads prior to polymer bumping. The typical metal thickness is 0.5-1.0 pm for Pd and 3.0-5.0 pm for Ni/Au. 

Flip-chip technology, as shown in Fig. 11.14, is similar to TAB technology in that successive metal layers are deposited on the wafer, ending up with solder-plated bumps over the device contacts. One possible configuration utilizes an alloy of nickel and aluminum as an interface to the aluminum bonding pads. A thin film of pure nickel is plated over the Ni/Al, followed by copper and solder. The copper is plated to a thickness of about 0.0005 in., and the solder is plated to about 0.003 in. The solder is then reflowed to form a hemispherical bump. The devices are then mounted to the substrate face down by reflow solder methods. During reflow, the face of the device is prevented from contacting the substrate metallization by the copper bump. This process is sometimes referred to as the controlled collapse process. 

Silicon dioxide, silicon nitride, silicon-oxy-ni trite and polyimides are commonly used in device passivation. These passivation layers are known to have excellent moisture and mobile ion barriers of the devices. As for the sodium ion barrier, silicon dioxide is inferior to silicon nitride. However, the use of phosphorous (a few weight percent, usually less than 6 %) doped silicon dioxide has greatly improved its mobile ion barrier property, A thin layer (in 1-2 um thickness) of one of these dielectric materials is deposited uniformly on the finished device, except at the bond pad areas for bonding. Most of these inorganics are deposited in one of the three major processes... 

Planar voids result in diminished bond strength and solder-joint fracture. This defect has been responsible for some product failures and recaUs.The root cause of the microvoids is generally believed to be the result of volatile organics incorporated during Ag plating, but there also seems to be a correlation between Ag thickness and Cu topology on the bond pad. 

The final layer is a 0.5 pm thick gold metal layer on top of Poly2 for wires, bond pads, bimorphs, and potentially as an optically reflective surface. The gold is deposited on top of a thin (20 nm) chrome layer to promote adhesion. It is not possible to deposit gold on top of the Polyl layer. For a flat mirror to be formed, the stress-induced curvature from the metallization should be comprehended in the design [13]. 

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