Vector hardware

Benchmarks of selected pieces of code run on the ASC and on scalar machines (CDC 7600, Cyber 174, IBM 360) are also included. These examples will illustrate not only the power of certain vector instructions but also the difference in programming styles required to take advantage of the ASC vector hardware. General guidelines for writing vector code will be summarized briefly. 

The ASC differs from the conventional scalar computer in that it is a pipeline computer with a full set of hardware vector instructions in addition to the standard scalar instructions. The vector hardware includes arithmetic operations such as add, subtract, multiply, divide, vector dot product, as well as vector instructions for shifting, logical operations, comparisons, format conversions, normalization, merge, order, search, peak pick, select, replace, MIN, and MAX. Although an ASC may have one to four pipes, the configuration described below will be that of the two pipe machine at NRL. 

In the drive to optimize use of available hardware to enable more robust simulations through increasing system size and simulation length, the optimization of MD algorithms for vector hardware has been extensively discussed in the literature, -203 vv ith considerable attention paid to the task of optimizing efficiency.204,20J provide some background to this effort because much of the work impacts subsequent parallel implementations. 

Vectorization A vector computer applies the same operation to different elements of the same array in parallel. To support vector hardware, compilers apply a series of transformations to expose loops that can be expressed as vector computations. Vectorization typically requires the compiler to determine that the execution of a particular statement in any iteration does not depend on the output of that statement in previous iterations. 

Mathematical models require computation to secure concrete predictions. Successes in relatively simple cases spurs interest in more complex situations. Somewhat specialized computer hardware and software have emerged in response to these demands. Examples are the high-end processors with vector architecture, such as the Cray series, the CDC Cyber 205, and the recently announced IBM 3090 with vector attachment. When a computation can effectively utilize vector architecture, such machines will out-perform even the most powerful conventional scalar machine by a substantial margin. Such performance has given rise to the term supercomputer. ... 

The NIPALS algorithm is easy to program, particularly with a matrix-oriented computer notation, and is highly efficient when only a few latent vectors are required, such as for the construction of a two-dimensional biplot. It is also suitable for implementation in personal or portable computers with limited hardware resources. 

For the purposes of presentation, the velocity held is usually presented at regular intervals. This new scheme is very efficient and incorporates a vector validation procedure, making it independent of operator intervention. The time it takes to compute a vector field depends on the computer hardware and it ranges from 350 mesh points per second on a PC 150 MHz Pentium to 1400 mesh points per second on a 200-megahertz dual Pro. 

The Enrolment Terminal (cf. Figure 12) uses the NASK Iris Module and BioBase Access Module. A separate application is developed that uses common elements of NASK biometrics modules, namely, the device library to control the hardware, and the algorithms library to process iris images and calculate iris features vectors. 

Now let s look in detail at each process, so that we can understand the NMR acquisition parameters needed to set up the experiment. After the pulse, we will follow through the hardware devices in a block diagram and try to understand a little about the NMR hardware. It turns out that processing of the NMR signal in the hardware is strictly analogous to the theoretical steps we will use in viewing the NMR experiment with the vector model, so it is essential to understand it in general. 

There are three Tektronix terminals that are emulated, the 4010, 4014 and 4027. The 4010 is a high resolution terminal with cross hair cursors for graphics input, the 4014 adds a hardware line patterns, choice of character sizes and user definable character sets with local storage for commonly used structures. The 4027 is a color raster terminal with 64 colors, 16 character fonts, as well as polygon and vector commands. 

It is worth pointing out that the vectorised code is written in standard FORTRAN. The CRAY FORTRAN compiler simply recognises the vectorisable loops and translates these into hardware vector orders. An inspection of the machine code thus generated revealed that very little was to be gained by hand coding the kernels into Assembly language. 

With the advent of vector processors over the last ten years, the vector computer has become the most efficient and in some instances the only affordable way to solve certain computational problems. One such computer, the Texas Instruments Advanced Scientific Computer (ASC), has been used extensively at the Naval Research Laboratory to model atmospheric and combustion processes, dynamics of laser implosions, and other plasma physics problems. Furthermore, vectorization is achieved in these programs using standard Fortran. This paper will describe some of the hardware and software differences which distinguish the ASC from the more conventional scalar computer and review some of the fundamental principles behind vector program design. 

Finally, most doubly or triply subscripted array operations can execute as a single vector instruction on the ASC. To demonstrate the hardware capabilities of the ASC,the vector dot product matrix multiplication instruction, which utilizes one of the most powerful pieces of hardware on the ASC, is compared to similar code on an IBM 360/91 and the CDC 7600 and Cyber 174. Table IV lists the Fortran pattern, which is recognized by the ASC compiler and collapsed into a single vector dot product instruction, the basic instructions required and the hardware speeds obtained when executing the same matrix operations on all four machines. Since many vector instructions in a CP pipe produce one result every clock cycle (80 nanoseconds), ordinary vector multiplications and additions (together) execute at the rate of 24 million floating point operations per second (MFLOPS). For the vector dot product instruction however, each output value produced represents a multiplication and an addition. Thus, vector dot product on the ASC attains a speed of 48 million floating point operations per second. 

Finally, Almlof and Taylor reviwed the implementation on vector-oriented hardware, while some of the chapters in the two volume series were dedicated to the MCSCF methodology. 

Nested Summation Symbols are ideal constructs for programming in a suitable hardware environment, for example using transputer boards [51] or any computing device with various CPU runnixig in parallel [62]. All operations attached to each vector k can be run in a separate CPU. Counting the times this can be done in... 

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