Silicon dioxide wafers

For some materials, the most notable being silicon, heating alone sufiBces to clean the surface. Commercial Si wafers are produced with a thin layer of silicon dioxide covering the surface. This native oxide is inert to reaction with the atmosphere, and therefore keeps the underlying Si material clean. The native oxide layer is desorbed, i.e. removed into the gas phase, by heating the wafer in UHV to a temperature above approximately 1100 °C. This procedure directly fonus a clean, well ordered Si surface. 

The potential of photolithography for the construction of protein microarrays has also been demonstrated (Mooney et al., 1996). For these experiments, antibodies were assembled in precise two-dimensional patterns on silicon wafers. This was accomplished by first forming a self-assembled monolayer of n-octadecyltrimethoxysilane (OTMS) on a silicon-dioxide... 

As an example of the latter technique, Volkman et al. demonstrated the feasibility of using spin-cast zinc oxide nanoparticles encapsulated in 1-dodecanethiol to fabricate a functional transistor.44 The zinc oxide was deposited on a thermally grown silicon dioxide layer on a conventional silicon wafer, with thermally evaporated gold source and drain electrodes. As reported, the process requires very small particles (3nm or less) and a 400 °C forming gas anneal. A similar approach was also reported by Petrat, demonstrating n-channel thin-film transistor operation using a nanoparticle solution of zinc oxide dispersed onto a thermally grown silicon dioxide layer on a conventional... 

Other classes of silanes, namely alkoxy, halogenated, and other silanes [3, 9], are known to react with —OH containing compounds, and, therefore, should also function as adhesion promoters or surface modifiers for —OH containing substrates. Texas Instruments, for example, employed a 2% xylene solution of phenyltrichlorosilane to provide resist image adhesion to various oxide wafer substrates [10]. References 3, 9, and 10 describe many of these materials applied to silicone dioxide substrates. As for HMDS treatment, ESCA evidence of reactions to verify covalent bonding to surface silanol groups will be provided in... 

The wafers were coated with silicon dioxide (400 nm thickness) and silicon nitride by low pressure chemical vapor deposition (LPCVD) alternately. The chips were fabricated by photolithography and etching. The catalyst (for the application Pt) was introduced as a wire (150 pm thickness), which was heated resistively for igniting the reaction. The ignition of the reaction occurred at 100 °C and complete conversion was achieved at a stochiometric ratio of the reacting species generating a thermal power of 72 W (Figure 2.28). 

The rapid mixer is composed of layers that are fabricated separately and then assembled together. The main four channel device, represented by the cartoon of Fig. 12.2, is etched through a 1-mm-thick silicon wafer using an anisotropic Bosch process RIE (Unaxis 770, Unaxis). The depth of this etch requires a thick mask. We use a 7 pm layer of PECVD silicon dioxide (GCI PECVD Group Sciences Incorporated, San Jose, CA). This mixer is sandwiched between two 100 pm thick poly(dimethylsiloxane) (PDMS) layers (Duffy et al, 1998), which contain channels in a T configuration. 

One commercial wafer deflection gauge is available, and is sketched in Figure 6. The degree of light reflection is used to indicate the amount of wafer deflection. The only difficulty with this technique occurs when relatively low stress films are measured. For normal films (i.e., thermal CVD silicon dioxide) and a stress of 109 dynes/cm2, a typical 100-mm silicon wafer (0.62-mm thick) with a 1-jum thick film will deflect 10 jum at its center. The Ionic Systems gauge claims a 0.03-pm sensitivity, so the typical stress can be measured readily. For smaller stresses 108 dynes/cm2, it may be useful to use a thinned wafer to make deflection measurements. 

There are a number of subtle effects that have to be considered when making thin film stress measurements on silicon wafers First of all, the crystal orientation of the wafer Influences the resulting stress. The same thermal CVD silicon dioxide film thickness on the same substrate indicates larger tensile stresses on (100)-oriented wafers as compared with (111 (-oriented wafers. 

The most commonly implemented and extensively investigated CMP steps are the preparation of planar premetal dielectrics (PMD) and interlayer dielectrics (ILD) films on wafer. Together they are labeled as oxide CMP, as they both use the same materials that are based on silicon dioxide. Both processes share the integration concerns in deposition, planarity, and defectivity. 

In essence, STI CMP and ILD CMP are in a similar category. They are both required to remove certain amount of silicon dioxide film from the wafer surface. They are both dominated by mechanical actions. Therefore, the particle characteristics of the slurry are very important. In general, the material removal rate is proportional to the particle size. In a study reported by Park et al. [35], over a wide range of experimental conditions the oxide removal rate decreased with decreasing abrasive size. As abrasive particles play a significant role in determining the overall removal rate and surface quality, it is important to examine the relative importance of the mean particle size and particle size distribution. 

The color of silicon dioxide is a function of its thickness. Color variation across the dies and the wafer indicates oxide thickness nonuniformity. Ideally, there should be no color variation over the same type of underneath structures. Global color variation across the wafer indicates a CMP uniformity problem. Local color variation at a structure level or arrays of structures within a die reveals a lack of planarization. There is a fine difference between planarization deficiency and nonuniformity. Nonuniformity is revealed in the form of a very gradual thickness variation over 10 mm or more. It is usually not pattern dependent. A rapid thickness variation across arrays of structures less than 5 mm wide is indicative of a planarization problem. This is a pattern-dependent... 

On patterned copper wafers, after CMP, the surfaces are covered mainly by dielectric and copper features. The large scratches on the dielectric such as TEOS oxide will have similar shatter mark characteristics as described in Section 17.2. The scratches on the copper lines or features, however, have a very different signature. As the copper is a soft material with large plastic deformation area, it is very easy to scratch copper (Fig. 17.41). The scratches on copper usually show well-defined continuous lines. A copper scratch can be very shallow and very narrow (Fig. 17.42). It is worthwhile to point out that the extent of damage by scratch is also a function of the underlying dielectric. As a low-fe dielectric is usually much more fragile than silicon dioxide, the damage on copper lines with low-fc dielectric may be more severe (Fig. 17.43). 

The feed gas enters the reactor at a rate of 3.74 SCMM (standard cubic meters per minute) and contains 22.0 mole% DCS and the balance N2O. In the reactor, the gas flows around the wafers, DCS and N2O diffuse into the spaces between the wafers, N2O is adsorbed on the wafer surfaces, and the adsorbed N2O reacts with gaseous DCS. The silicon dioxide formed remains on the surface, and the nitrogen and hydrogen chloride go into the gas phase and eventually leave the reactor with the unconsumed reactants. The temperature and absolute pressure in the reactor are constant at 900°C and 604 millitorr. 

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