TEOS Oxide

TEOS oxide was tested first as a CVD dielectric in order to examine the compatibility of the pentacene and the TEOS oxide. This dielectric offers a conformal deposition on lateral and vertical surfaces at high deposition rate but 

The investigations of TEOS oxide use a gate dieleetrie that is deposited at a proeess pressure of 0.2 mbar. By ellipsometry, the film thiekness eould be determined to be 120 nm. The surfaee of the dieleetrie was investigated by AFM and exhibited a smooth surfaee with a roughness of 1 - 3 nm rms. 

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Fig. 5. Etching rate of some back-end materials in different nonoxidant cleaning mixtures adjusted to etch 5 nm of PECVD TEOS oxide in 10 min.

TEOS oxide selected as the back-end reference material. Figure 5 indicates the etching rates of the different back-end materials in these mixtures. 

The etching rate of PECVD silicon nitride is comparable to PECVD TEOS oxide. Ti, TiN, and W present an acceptable etching rate whatever the pH. In the presence of copper, only HF-based chemistries can be used. For Al/Cu none of the tested mixtures are suitable. 

Fig. 14. Evolution of alumina particle removal efficiency from PECVD TEOS oxide as a function of pH. As expected, better results are obtained in areas A and B.

Both silicon oxide and alumina slurries can be efficiently removed on PECVD TEOS oxide or silicon nitride substrates in a conventional SCI or in a SCI without any water peroxide in the case of outcropping tungsten (see Fig. 5). When water peroxide is not present to continuously regrow a protective oxide layer, OH species can etch the silicon. In the latter case, the backside of the wafer must therefore be protected with a nitride or oxide layer to avoid a severe silicon roughening effect. Nevertheless to achieve the same particle removal efficiency obtained with a scrubber, power mega-sonics also have to be used (see Fig. 18). 

Fig. 18. PECVD TEOS oxide slurry removal efficiency in ammonia-based chemistries (0.25, 6) performed at 55°C during 10 min. Diluted ammonia with megasonics gives results as good as the scrubber.

Fig. 19. Alumina slurry removal elficiency in HF mixtures on PECVD TEOS oxide. Behavioral differences between alumina particles and slurries and efficiency of a specific HF- compatible very-high-power megasonics tank. (Direct Coupling system from SubMicron Inc.)...

Fig. 23. Example of damaged layer estimation in PECVD TEOS oxide as measured by ellipsometry using 0.1% HF and [0.25, 6] NH4OH 70°C.

One of the metrology issues with the STI process is that the process utilizes three layers of different materials (1) thin thermal oxide (less than 200 A), (2) nitride (approximately 1500 A), and (3) the TEOS oxide above the active regions (see Fig. 7). Ideally, the CMP process polishes the TEOS oxide and stops at the nitride. In reality, after the polish, either a very thin residual TEOS oxide is present or the TEOS is completely gone and the nitride thickness is being measured. This poses some problems in the setup... 

FIGURE 13.19 Removal rates of TEOS oxide and CVD silicon nitride with proline ceria slurry over pH range of 6-11. Ceria was 1 wt% with 2 wt% of L-proline. 

On patterned copper wafers, after CMP, the surfaces are covered mainly by dielectric and copper features. The large scratches on the dielectric such as TEOS oxide will have similar shatter mark characteristics as described in Section 17.2. The scratches on the copper lines or features, however, have a very different signature. As the copper is a soft material with large plastic deformation area, it is very easy to scratch copper (Fig. 17.41). The scratches on copper usually show well-defined continuous lines. A copper scratch can be very shallow and very narrow (Fig. 17.42). It is worthwhile to point out that the extent of damage by scratch is also a function of the underlying dielectric. As a low-fe dielectric is usually much more fragile than silicon dioxide, the damage on copper lines with low-fc dielectric may be more severe (Fig. 17.43). 

Tungsten polish rate and selectivity to TEOS oxide in slurries of alumina abrasive plus an oxidizer as a function of abrasive and oxidize concoitration. (From Ref. (24).)... 

The effect of pH on patterned TEOS oxide wafers was also investigated using the MIT CMP Characterization Mask Set pitch mask [1]. The pitch mask is a 6 x 6 array of various equal width lines and spaces. The lines and spaces have widths ranging from 2 pm to 1000 pm. The 12 mm pitch pattern was first created in photoresist across the entire wafer. The expiosed oxide was plasma etched to a depth of about 7000 A below the surface. This created an array of 36 sub-arrays with equal width lines and spaces so that half the area was lines and the other half spaces. The wafers were pwlished with silica slurry at 3 different pH values. The oxide thickness at the plateau area (starting surface of the oxide) for 10 sub-patterns of line widths 40,60,80,100,125, 150, 180, 200,250, and 500 pm were measured before and after CMP. The measurements were made in each sub-array in increasing order of line/space width. Five dies were measured along the diameter of the wafer. 

The effect of temperature of slurry containing ceria particles (average diameter 440 nm and lEP 8.5), on the removal rates of TEOS oxide and silicon nitride was found to be weak as seen in Figure 1. This is similar to the effect of temperature of a silica based slurry on silica pK)lishing in the temperature range of 20-50 °C for the slurry with the pad maintained between 25-30 C [2]. The pad hardness decreases with an increase in temperature [2] and the associated reduction in removal rate may have compensated for any increased chemical removal caused by the increased temperature. 

Figure I. Variation of polish rate with temperature for TEOS oxide and silicon nitride. The slurry was 5 wt % ceria, 440 nm diameter, lEP 8.5 with pH adjusted to 10. 

Figure 2. Variation of policing rate of TEOS oxide and silicon nitride with pH for SS-25 (1 1) using an IClOOO/SuhaTV stacked pad.

Figure 4. Effect of pH of ceria slurry on TEOS oxide and silicon nitride polish rate. 

There were two types of wafers used in this experiment blanket test wafers and fully integrated production wafers. The blanket test wafers used in this experiment were P(IOO) silicon deposited with 7500A of TEOS oxide followed by a sputtered TiN adhesion layer and a deposited SOOOA W film. The tungsten film used in this experiment was deposited in an Applied Materials CENTURA reactor, using WFe reduced with SiHt and H2. After W deposition, W CMP was performed using different hardware and process parameters. 

Different layers deposited by low pressure chemical vapour deposition (LPCVD) or by plasma enhanced chemical vapour deposition (PECVD) were examined as further inorganic gate dielectrics. Insulating layers of tetraethylor-thosilicate (TEOS) oxide, deposited by the thermal pyrolysis of the vapour... 

Figure 18.5 Output characteristic of an OFET with 1000 pm channel width and 5 pm channel length on a 120 nm thick TEOS oxide layer. The thickness of the pentacene film is about 60 nm, deposited at a substrate temperature of 60 °C and a deposition rate of 0.3 nm/s at 7.4 X 10 mbar chamber pressure.

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