Polysilicon etching

Since doping affects the etch rate of polysilicon, we investigated the etch rate characteristics of each gas used in the etch process (Table 1). We discovered that, the polysilicon etch rate with SF6 was independent of doping effects. To minimize the isotropic etch characteristics of SF6 in the B.T step(3), we used HBr, which is a well known polymer forming gas, with a SF6 HBr ratio of 1 0.75. With this new process, vertical profiles were obtained after the B.T step, in both types of polysilicon. At the end of the B.T step, the remaining polysilicon thickness in the n-type was comparable to the p-type and was less than the amount of polysilicon after the B.T step In the conventional process (Fig. 2-a 2-b). Also, the later the EP in the M.E step, the thinner was the remaining polysilicon in the p-type, thus... 

Eray Aydil, Theoretical and Experimental Investigation of Chlorine Glow Discharges and Polysilicon Etching, Ph.D. Thesis, University of Houston (1991). 

The fundamental kinetics and transport properties of plasma processes are reviewed and applied to polysilicon etching in Cla discharges. The relative neutral flux, ion flux, and ion energy is critical in controlling the directionality of the etching process. The electron density and energy have been estimated from electrical impedance measurements of Cl2 discharges. 

Note LD PSi, low-density polysilicon etch, Ct/HBr etch chemistry (15i3 m Torr) HD PSi, high-density polysilicon etch, Cb/HBr etch chemistry (10 mTorr) Oxide, high-density oxide etch, C2F6 etch chemistry (5 mTorr). 

Polymer Oxide etch (CHF3) Polysilicon etch (CI2) Metal etch (SFe)... 

Oxide etch rate (nm/s) Oxide etch selectivity Polysilicon etch rate (nm/s)... 

The polysilicon (poly) gate etch process is shown schematically in Fig. 13.12. Photoresist (PR) etching and polysilicon etching are the most critical batch steps for... 

Chang J P, Arnold J C, Zau G C H, Shin H-S and Sawin H H 1997 Kinetic study of low energy ion-enhanced plasma etching of polysilicon with atomic/molecular chlorine J. Vac. Sc/. Technol. A 15 1853-63... 

The easiest way to have different parts of the electrode surface under different bias is to disconnect them by an insulator. This method is elucidated by an experiment in which an electrochemical etch-stop technique has been used to localize defects in an array of trench capacitors. In a perfect capacitor the polysilicon in the trench is insulated from the substrate whereas it is connected in a defect capacitor, as shown in Fig. 4.15 a. If an anodic bias is applied the bulk silicon and the polysilicon in the defect trench will be etched, while the other trenches are not etched if an aqueous HF electrolyte is used, as shown in Fig. 4.15b. The reverse is true for a KOH electrolyte, because the only polysilicon electrode in the defect trench is passivated by an anodic oxide, as shown in Fig. 4.15 c. 

Another possibihty to improve the temperature homogeneity is to introduce an additional polysiHcon plate in the membrane center. The thermal conductivity of polysilicon is lower than that of crystalline siHcon but much higher than the thermal conductivity of the dielectric layers, so that the heat conduction across the heated area is increased. Such an additional plate constitutes a heat spreader that can be realized without the use of an electrochemical etch stop technique. Although this device was not fabricated, simulations were performed in order to quantify the possible improvement of the temperature homogeneity. The simulation results of such a microhotplate are plotted in Fig. 4.9. The abbreviations Si to S4 denote the simulated temperatures at the characteristic locations of the temperature sensors. At the location T2, the simulated relative temperature difference is 5%, which corresponds to a temperature gradient of 0.15 °C/pm at 300 °C. 

A representative sample of terpolymers was exposed to a variety of etchants for polysilicon and silicon dioxide, and the results are given in Table V. The ratio of the etch rate of the substrate to the etch rate of the resist must be at least 2 1 for the resist to be a viable etch mask. Inspection of Table V, shows that the materials examined are unacceptable for only the QFj — CF3CI (4 1) plasma. The etch rates are comparable to those for PMMA the a-keto-oxime exhibits essentially no effect on that rate and the nitrile affords a slight decrease in the plasma etch rate. The etch rates of some commercially available materials are shown for comparison. 

Step 7. A blanket layer of polysilicon and pattern (mask 2), such that the resist covers only the polysilicon that is to become the gate, is deposited. All exposed polysilicon is etched away. 

Polysilicon (used as a sensor heater) was delineated by etching in a SFg plasma. A 1 pm layer of CVD Si02 was deposited, and a 100 nm tin oxide film was subsequently sputter-deposited (Figure 1b). 

The tin oxide thin film was patterned by reactive ion etching (RIE) using either SiCl or 1% H2 in N2 as the etch gas. The polysilicon contact holes were opened by wet-chemical etching in buffered hydrofluoric acid (BHF). A double-layer metallization (Cr -50 nm plus A1 -1 pm) was done by electron beam evaporation to form the electrical interconnection (Figure 1c). 

Polished or unpolished polysilicon (by low-pressure CVD at 620°C) is another etch mask option. Utilizing 2.5-pm-thick unpolished polysilicon, a maximum etch depth of 160 pm was reached using a HF/H20/HN03 (6 40 100) solution. Further etching causes large pits (1.5-2.2 mm dia.) to form on the glass. With polished poly silicon (1.5 pm thick), etch depth up to 250 pm can be achieved. When amorphous Si is used as the etch mask, a maximum etch depth of 170 pm can be reached [123]. 

To reduce expense, efforts are made to exploit integrated thin film technologies. For example, arrays have been produced via thin film deposition of the pyroelectric onto a sacrificial layer, e.g. a suitable metal or polysilicon, which is then selectively etched away. Thermal isolation of the pyroelectric element is achieved through engineering a gap between it and the ROIC silicon wafer. Yias in the supporting layer permit electrical connections to be made between the detector and the wafer via solder bonds. Imaging arrays have been produced in this way incorporating sputtered PST and sol-gel formed PZT films. 

F. H. Bell and O. Joubert, Polysilicon Gate Etching in High Density Plasmas. 5. Comparison between Quantitative Chemical Analysis of Photoresist and Oxide Masked Polysilicon Gates Etched in Hbr/Cl-2/0-2 Plasmas, J. Vac. Sci. Technol. 5 15, 88-97 (1997). 

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