Planarization technologies

Among numerous planarization technologies, CMP provides a global planarization of topography with a low post-planarization slope [97,98]. It can also dramatically reduce topographical variations to a degree not possible with any other planarizing process [97,99,100]. 

GaAs, CdTe and HgCdTe are deposited epitaxially on a silicon substrate in US-A-4910154. If islands of individual detector elements are formed, the deposited layers will have a combined thickness which makes it difficult to interconnect the detector elements with corresponding silicon circuitry due to the steep sides of the detector elements. It is therefore proposed to grow the GaAs, CdTe and HgCdTe layers in recesses formed in the silicon substrate, and interconnect with a planar technology. 

Hopefully, the work discussed within will help to ensure that the next 10 years of planarization technology development will be as fascinating, interesting, and useful as the first 20 have been. 

One effective method of cost reduction would be to reduce the operating temperature, and in this respect four types of stack have been developed. These include (i) a tubular design, with the tubes closed at one end (Westinghouse prototypes) or opened at both ends (ii) a planar technology (iii) a segmented series arrangement of individual cells (Rolls-Royce) and (iv) a monolith concept (Argonne National Laboratory). 

The manufacturing process for fabricating rod-shaped heaters is similar to those used in planar technology, because the active heater pattern is typically printed on an alumina tape that is wound around a pre-fired alumina rod or tube. The alumina allows sintering at low 02 pressure and therefore inexpensive tungsten is the typical heater material. However, leaks and the residual porosity of the materials lead to a continuous increase in electrical resistance, caused by slow tungsten oxidization. 

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