Patterned Wafers

To understand the impact of a CMP process on a certain product with a unique integrated circuit pattern, it is desirable to measure areas with different feature sizes and shapes. Since CMP polish rate may be affected by pattern density, areas encompassing various features should be included in the measurement program. The within-die thickness nonuniformity will indicate the planarization capability of a CMP process. 

To measure the final oxide thickness in the PMD process, the measurement sites can be set up over field oxide or over the polysilicon interconnections (see Fig. 6). However, since there are fewer variables in measuring over the field oxide, and the field oxide process is relatively well established, the PMD thickness is more accurately measured over the field oxide. If the measurement is over the polysilicon, the resultant PMD thickness measured can be affected by the deposited polysilicon thickness, the polysilicon doping, and the field oxide thickness variation, while if the measurement is over the field, the PMD thickness is affected only by the field oxide thiekness. 

For the ILD process, it is less feasible to continue measuring over field oxide, because multiple oxide layers are present (also see Fig. 6). The true thickness and thickness uniformity of the particular level of an ILD proeess can be confounded by the presence of the underlying previous layers. Thus, after the first metal process, it is preferable to measure the oxide thickness directly on a metal line. 

One of the metrology issues with the STI process is that the process utilizes three layers of different materials (1) thin thermal oxide (less than 200 A), (2) nitride (approximately 1500 A), and (3) the TEOS oxide above the active regions (see Fig. 7). Ideally, the CMP process polishes the TEOS oxide and stops at the nitride. In reality, after the polish, either a very thin residual TEOS oxide is present or the TEOS is completely gone and the nitride thickness is being measured. This poses some problems in the setup 

Defect detection on a wafer after CMP can be accomplished by a laser scanning technique and/or by a digital image comparison technique. Both types of tools are widely used in the industry. However, neither is sufficient 

---

The patterned wafer might next be placed in a diffusion furnace, where a first doping step is performed to deposit phosphoras or boron into... 

In Section II, we focus first on wafer-scale models, including macroscopic or bulk polish models (e.g., via Preston s equation), as well as mechanistic and empirical approaches to model wafer-scale dependencies and sources of nonuniformity. In Section III, we turn to patterned wafer CMP modeling and discuss the pattern-dependent issues that have been examined we also discuss early work on feature-scale modeling. In Section IV, we focus on die-scale modeling efforts and issues in the context of dielectric planarization. In Section V, we examine issues in modeling pattern-dependent issues in metal polishing. Summary comments on the status and application of CMP modeling are offered in Section VI. 

As mentioned, the solution (oxidizer) plays a difficult and dominating role in the metal slurry. On one hand, the selectivity between different metal layers should be close to unity. On the other hand, the selectivity between metal and oxide should be as large as possible. Further, on one hand, the polish rate for metal needs to be higher than 3000 A/min. On the other hand, dishing or plug recession must be minimized at the metal areas on the patterned wafers. 

Plug recess and oxide erosion between the H2O2 (silica as abrasives) and the HjIOg (mixture of different abrasives) based slurries are also evaluated on patterned wafers. The same polisher (rotating), recipe, and pad (ICIOOO/... 

Fig. 8, Schematic diagram of (top) asperity contact during CMP, (middle) die-scale asperity contact for patterned wafer with topography height x and (bottom) die-scale asperity contact for patterned wafer with topography height x/3.

The surface composition of the uncoated, patterned wafer was analyzed by Auger spectroscopy. Line quality and surface detail at each key process step were examined by scanning electron microscopy using samples overcoated with lOOA of a platinum/gold alloy. 

FIGURE 2.21 (a) Wafer-etch geometry, (b) An image of the slurry layer between a patterned wafer and a Fruedenburg FX9 polishing pad. 

FIGURE 5.6 Comparison of patterned wafer profile and step height reduction efficiency (SHRE) for polishing on ICIOOO and NCP pads (a) Wafer profile before polishing, (b) wafer profile after polishing, (c) SHRE on ICIOOO pad, (d) SHRE on NCP pad. 

FIGURE 5.7 Comparison of normalized patterned wafer step height reduction efficiency (SHRE) for polishing on ICIOOO and various NCP pads. 

When dishing occurs in a patterned wafer, the ILD beside the dished area polishes faster than the ILD in isolated field regions. The ILD height difference between patterned and field areas, shown in Fig. 5.20, is called erosion. Experimentally, erosion depends on the pattern density. 

There are several pressures relevant to polishing of patterned wafers. Pm and PiLD are the pressures on the metal and ILD of a wafer with pattern density 9, for applied pressure P and with AP = Pild Pm- Because the metal is recessed relative to the ILD, the pad expands into the cavity and exerts less pressure on the metal than on the ILD. The total force P on a wafer of areaA-w is the sum of pressures on the metal and ILD areas, F = PA-w = Pm A-w + f iLoCl d)Aw It follows that Pm = P — (1 — 0)AP while Pild = P + dAP and... 

Thus CMP pads play an important role in dishing of patterned wafers. The model presented here parameterizes CMP pads using Young s modulus, Poisson s ratio, and pad thickness plus an unusual fcstretch term. Control of these parameters could lead to improvements in dishing and erosion outcomes during polishing. 

Finally, after development of the two-step model and application of the model to blanket wafer polishing, we describe how the model may be applied to patterned wafer polishing and how the latter may differ from blanket polishing. 

FIGURE 6.8 (a) Blanket copper polishing data from a commercial tool, (b) Pad thermal data from both blanket and patterned wafer... 

FIGURE 7.23 The overall average overburden copper thickness and step height of 100 pm copper in the 50 % metal density region on a SEMATECH 854 patterned wafer (from Ref. 109). 

FIGURE 11.30 A typical electric current trace for Cu-clearing process on a patterned wafer, showing drop in current upon Cu clearance (from Ref. 34). 

Figure 13.2 illustrates the cross section of a representative patterned wafer design for the evaluation of a direct STI CMP process or consumables such as slurry and pad. An ideal STI process should remove all overburden oxide and stop at the silicon nitride layer without any dishing and nitride loss, as shown in Fig. 13.3. Figure 13.4 is a representative STI patterned wafer layout [9]. 

FIGURE 13.2 A cross-sectional view of a representative patterned wafer for STI... 

FIGURE 13.3 A cross-sectional view of an ideally polished STI patterned wafer. 

FIGURE 16.12 STI patterned wafer surfaces in the DRAM process. 

Galvanic corrosion tends to occur when two metals with different electrochemical potentials are electrically connected and exposed in an electrolyte. As a result, the less noble metal will suffer from accelerated corrosion [58]. When excess copper is polished away by copper CMP, copper and barrier metal are exposed to the CMP slurry simultaneously. Copper and barrier metal have different electrochemical potentials and thus trigger galvanic corrosion at the interface between copper and barrier metal at a certain kind of slurry composition. In this galvanic corrosion, electrons are transferred from titanium anode to copper cathode. During overpolishing of the patterned wafer, titanium near the copper structure is recessed owing to dissolution (Ti Ti -I- 2e ) and Cu " ions are preferentially deposited onto... 

---