Wafer polishing

Fig. 4.3 SEM micrograph of the rear side of an n-(lOO) Si wafer polished on one side. The presence of inverted truncated square pyramidal stmctures fuUy covering the surface can be observed. This pyramidal texturing was attributed to the combination of anisotropic etching of the sdicon and to hydrogen bubbles evolved during the etching reaction. (Reprinted from [23] Copyright 2009, with permission from Elsevier)...

The steam reformer is a serpentine channel with a channel width of 1000 fim and depth of 230 fim (Figure 15). Four reformers were fabricated per single 100 mm silicon wafer polished on both sides. In the procedure employed to fabricate the reactors, plasma enhanced chemical vapor deposition (PECVD) was used to deposit silicon nitride, an etch stop for a silicon wet etch later in the process, on both sides of the wafer. Next, the desired pattern was transferred to the back of the wafer using photolithography, and the silicon nitride was plasma etched. Potassium hydroxide was then used to etch the exposed silicon to the desired depth. Copper, approximately 33 nm thick, which was used as the reforming catalyst, was then deposited by sputter deposition. The reactor inlet was made by etching a 1 mm hole into the end... 

The first CMP tools, based on rotational platen silicon wafer polishing tools, had low throughput values (10 to 18 wfr/hr). Since the implementation of these first-generation tools for polishing, CMP tool design has... 

A polish technology that is just emerging from development by several CMP capital equipment suppliers is the pad feed polisher. This equipment is based on some fairly recently developed polish pad rolls. These polish pads are in a roll similar to 35-mm camera film. The pad is fed out to the wafer polish table, a wafer is polished, the pad is conditioned, the pad is incremented forward, and then the next wafer is polished. 

Successful polishing with such a methodology strongly relies on the pad characteristics being consistent from beginning to end. This method is particularly useful for pads with very consistent first polishes, but whose characteristics degrade rapidly with subsequent wafer polishes. 

Aside from the basic approach to polishing, the most critical component of a CMP tool is the wafer earrier. As with CMP tools, wafer carriers have evolved from roots in lens grinding and in the silicon wafer polishing industries to meet requirements specific to polishing silicon-based integrated circuits. 

TXRF Metal Surface Concentrations for Wafers Polished with Various Slurries,... 

IR spectra were obtained on a Model 10MX Nicolet Fourier Transform infrared spectrometer. IR films were spin-coated from polymer solutions in chlorobenzene on either KBr discs or silicon wafers polished on both sides. The samples were baked in vacuum at 90 C for at least 1 hour to ensure solvent removal. Film thicknesses were approximately 1 jtm, sufficient to remove interference fringe effects from the spectra. 

Inaba T. Wafer polishing apparatus with retainer ring. US patent 6,033,292. 2000 Mar 7. 

When MRR of oxide wafer polishing on porous ICIOOO pad and on nonporous NCP pad is compared, it shows that MRR on nonporous NCP pad is slightly lower than that on porous ICIOOO pad, and WTWNU of MRR is comparable for NCP and ICIOOO pads (see Fig. 5.4). The WIWNU of MRR on NCP pad is much lower than that on ICIOOO pad. This demonstrates better... 

FIGURE 5.4 MRR variation from wafer to wafer (WTWNU) 100 oxide wafers polished on NCP pad (lower line with diamond marker) versus polished on ICIOOO pad (upper line with square marker). 

FIGURE 5.9 Normalized defectivity number comparison of Cu blanket wafers polished with first-step Cu slurries on ICIOOO pad and various NCP pads. 

FIGURE 5.24 MRR comparison of oxide wafer polishing on particle-containing pad with DI water and on IC1400 pad with fumed silica slurry at pH = 10.8 [81]. 

Finally, after development of the two-step model and application of the model to blanket wafer polishing, we describe how the model may be applied to patterned wafer polishing and how the latter may differ from blanket polishing. 

Topography planarization differs in several respects from blanket wafer polishing. Topography height variations over the wafer surface induce variations in contact local pressure high areas have higher contact pressure, and low areas may see little or no contact pressure. At equilibrium, the integral of the contact pressure over the wafer surface must equal the applied load. 

FIGURE 7.20 Removal rate versus downforce on 8" Cu blanket test wafers polished at 75/65 rpm table/carrier speed and 200ml/min slurry flow rate on Strasbaugh u-Hance polisher. Diamond data points indicate the removal rate values with the organic particles, and square data points denote removal rate values for silica particles, both polished under identical formulation and abrasive concentration (from Ref. 110). 

FIGLfRE 7.22 Representative surface quality image of Cu blanket test wafer polished with a slurry consisting of organic abrasive particles. Surface roughness RMS value of... 

FIGURE 12.13 Ellipsometric measurement of post-CMP film thickness on two wafers, polished with different process parameters, showing center-to-edge polish rate nonuniformity. 

FIGURE 13.10 (a) SEM cross-sectional view of a wafer just after polishing with HSS BKM 2 shows minimal SiN loss and minimal dishing, (b) SEM cross-sectional view of wafer polished with HSS BKM 2 just after SiN strip shows a nominal and consistent step height. 

FIGURE 13.31 Representative defect counts for STI wafers polished with imation slurry conditioner. STI-1 is a ceria-based slurry and STI-2 is a silica-based slurry. 

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