Interlevel dielectric layer

Fig. 6 Cross-section of a three-level metal device showing the trench isolation, W plugs, metal, and interlevel dielectric layers. (View this art in color at www.dekker.com.)...

Passivation layers, multilayer resist stacks, diffusion barriers, interlevel dielectrics, side-wall spacers, trench masks, oxidation masks, etc., in semiconductor devices. 

Pattern dependency concerns arise at two levels in STI CMP [67] during the oxide overburden polish phase, and when the nitride layer is exposed. In the first stage, the process is similar to interlevel dielectric (ILD) CMP and the characterization and modeling methodologies presented in the previous section are applicable. Once the nitride is exposed, two different materials exist at the same level, and pattern dependency manifestation is more complex. 

The function of the interlevel dielectric of the multilevel structure is three-fold (1) it must provide planarization of underlying topography while allowing high resolution patterning of via holes necessary for contact between metal layers, (2) it must provide insulation integrity, and (3) it must contribute minimally to device capacitance. 

The type of adhesion dealt with in the examples in the second paragraph above and Fig. 1 is mechanical or structural while for the lithographic resist adhesion requirements described in this paper a more practical definition of adhesion, one first proposed by Mittal [16], is being referenced and used. Resist patterning layer-substrate adhesion is required only to process or pattern a particular device layer. After the circuit layer is patterned, the resist layer is removed and does not become an integral part of the circuit, as opposed to a PI interlevel metal dielectric layer which does. As such, it is not required to possess high mechanical adhesion strength. In fact, the resist layer must be quantitatively removed after the circuit required layer has been patterned. If the resist layer adheres too well and becomes difficult to remove, it actually interferes with successful circuit fabrication. 

Silicon Nitride. Silicon nitride produced by high-temperature (>700 °C) CVD is a dense, stable, adherent dielectric that is useful as a passivation or protective coating, interlevel metal dielectric layer, and antireflection coating in solar cells and photodetectors. However, these applications often demand low deposition temperatures (<400 °C) so that low-melting-point substrates or films (e.g., Al or polymers) can be coated. Therefore, considerable effort has been expended to form high-quality silicon nitride films by PECVD. 

When used as an interlevel dielectric, even greater demands are placed on the polyimide. Because integrated circuit processing includes as a final step a metal sinter at 400 C, the interlevel insulator film must withstand such exposures without degradation of electrical, chemical, or mechanical properties. In addition, the deposition, cure, and etch process must provide for reliable interconnection between the metal layers above and beneath the film (the "via contact") [8]. Issues of ion motion, moisture uptake, and electrical conduction both in bulk and at interfaces must also be considered carefully. 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

To achieve successful Cu interconnects, it is essential to deposit effective barrier layers to avoid the oxidation and diffusion of Cu into interlevel dielectrics such as Si02. Both oxidation and diffusion of... 

Spin-on glass (SOG) films are desirable as an interlevel dielectric because of their inherent ability to planarize underlying topography. Depending upon the film thickness obtainable and the material characteristics, SOG films can be utilized either as a stand-alone interlevel Insulation layer or as a smoothing layer in conjunction with conventional CVD dielectric layers. The various schemes possible with the application of SOG films in interlevel insulation are illustrated in Figure 1. 

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